• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.2
• /
• pp.155-167
• /
• 2015

An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20", 30", 40" FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a $0.13{\mu}m$ process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.

• Journal of Digital Contents Society
• /
• v.19 no.4
• /
• pp.779-787
• /
• 2018

This study delves into how the equalizer can compensate for a sound pressure of lost frequencies. The targeted audiences are senior citizens who have difficulties hearing high-frequency because of a decline of audio frequency. Through investigations, this study confirms that the reason why reduction of high-frequency hearing increases depending on senescence. By considering the features of audio frequency of senior citizens, it also clarifies the necessity of equalizer reflecting features of audio frequency for the senior citizens, which have dramatically increased in Korea. There are application programs having functions, which provide several options of equalizer setup that people can adjust it depending on their own audio frequency. Some of them provide different equalizer setup depending on age. This study, however, reveals that they are not fully enough to compensate for the range of hearing loss of the senior citizens. Therefore, by pointing out limitations of existing functions and suggesting improvements, this study explores the way of improvements that enhance the sound transmissions of digital media contents for senior citizens.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.3
• /
• pp.300-311
• /
• 2016

The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.1132-1136
• /
• 2005

In this paper, adaptive equalizer receiver for a turbo code direct sequence code division multiple access (DSCDMA) by using least mean square (LMS) adaptive algorithm is presented. The proposed adaptive equalizer is using soft output of decision feedback adaptive equalizer (DFE) to examines the output of the equalizer and the Log- maximum a posteriori (Log-MAP) algorithm for the turbo decoding process of the system. The objective of the proposed equalizer is to minimize the bit error rate (BER) of the data due to the disturbances of noise and intersymbol interference (ISI)phenomenon on the channel of the DS-CDMA digital communication system. The computer program simulation results shown that the proposed soft output decision feedback adaptive equalizer provides a good BER than the others one such as conventional adaptive equalizer, infinite impulse response adaptive equalizer.

• Journal of Broadcast Engineering
• /
• v.8 no.2
• /
• pp.153-162
• /
• 2003

This paper describes a structure of adaptive equalizer to improve reception performance of ATSC digital television (DTV) for 8-VSB receivers. There are many strong and dynamic echoes affecting reliable reception of DTV signal. Conventional DFE based least mean square (LMS) algorithm is readily implemented and has good Performance. There are still problems to be solved, however, in handling strong echoes and indoor reception. In this paper, structure of adaptive equalizer to mitigate these Problems in strong multipath interference conditions and indoor reception environment is first presented. Methods to reduce error propagation effects on DFE and initialization scheme of filter coefficients for fast convergence are then introduced. Computer simulation results prove that an adaptive equalizer with proposed design methods can combat with Brazil Ensemble and the Threshold of Visibility(TOV) is improved.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.3
• /
• pp.387-393
• /
• 1987

The introduction of a digiral subscriber loop transmission system necessitates an optimized line interface solution. To meet this objective an adaptive line equalizer has been developed. The equalizer can be compensated up to 42 dB line loss at 200KHz, and operated up to 3.2 Km transmission length (0.4 mm\ulcornercable)at a rate of 400Kb/s. This has been builted using a variable \ulcorner equalizer to compensate a frequency-attenuation characteristics of metallic cable, an AGC (automatic gain control) circuits with simple control algorithm, and various filters to minimize a transmission constraints over subscriber loop. The purpose of this paper is to present a short description of a design of the adaptive line equalizer with a summary of implementation results. Some design concepts and considerations which results in an implementation of the equalizer are also given.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.12 no.5
• /
• pp.777-786
• /
• 2001

In this paper, as one of countermeasure techniques for a frequency selective fading, a digital slope equalizer(DSE) for 64-QAM digital radio relay system is analyzed in terms of principle, channel modeling, and digital implementation. Also computer simulations have been performed for DSE with a complex 13-tap adaptive time domain equalizer chip. It is shown that about 4.5 dB improvement in system signature can be obtained at the channel edge, and a variety of simulated results are reviewed in view of DSE modeling limit, operating frequency, control coefficient, signal constellation, and system signature. Finally, the functions of DSE chip confirmed up to 61 MHz clock operation are illustrated.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.899-902
• /
• 1999

In this paper, we designed a equalizer that moved the multipath of channel in 8-VSB transmission receiver. After doing the initial equalization with "LMS(Least Mean Square)"aigorithm. this equalizer used "Stop-and-Go" algorithm. Because of estimating SER(Symbol to Error Ratio) every a training sequence, this can positively cope with transformation of channel and because of using fast clock than symbol-clock(10.76 MHz), we are able to reduce a multiplier.

• Proceedings of the Optical Society of Korea Conference
• /
• 2000.02a
• /
• pp.56-57
• /
• 2000

In this paper, DFE with feedforward section(FDFE) is used to mitigate ISI and improve BER generated in the course of storage and retrieval of high-density 2-dimensional data in digital holographic memory system. From the result of experiment, BER performance of DFE with feedforward section is improved about 37% than binary-decision course by direct thresholding.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• v.2 no.3
• /
• pp.174-178
• /
• 2002

This paper discusses a blind equalization technique for FIR channel system, that might be minimum phase or not, in digital communication. The proposed techniques consist of two parts. One is to estimate the original channel coefficients based on fourth-order cumulants of the channel output, the other is to employ RBF neural network to model an inverse system fur the original channel. Here, the estimated channel is used as a reference system to train the RBF. The proposed RBF equalizer provides fast and easy teaming, due to the structural efficiency and excellent recognition-capability of R3F neural network. Throughout the simulation studies, it was found that the proposed blind RBF equalizer performed favorably better than the blind MLP equalizer, while requiring the relatively smaller computation steps in tranining.