• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.9
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• pp.974-978
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• 2003

The down-converter of the WCDMA Digital Optic Repeater is developed. Based on the system specifications, the structure of the down-converter is accomplished and its block diagram is drawn. The down-converter is implemented according to these block diagrams. Subsequently a low pass filter, an automatic level controlled attenuator, a frequency synthesizer and other components for the down-converter are designed and implemented, and a main board to integrate these modules is also manufactured. To reduce the noise floor of system and suppress the RF spurious noise, a PCB layout is performed carefully. For each module consisting of the down-converter and the entire system, the performance tests are accomplished to check the performance about the specifications.

• ETRI Journal
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• v.26 no.6
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• pp.555-559
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• 2004

We propose an efficient digital IF down converter architecture for dual-mode WCDMA/cdma2000 based on the concept of software defined radio. Multi-rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual-mode receiver for WCDMA and cdma2000. A sub-sampled digital IF stage was proposed to support both WCDMA and cdma2000 while lowering the sampling frequency. Use of a CIC filter and ISOP filter combined with proper arrangement of multi-rate filters and common filter blocks resulted in optimized hardware implementation of the front end block in 292k logic gates.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.5
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• pp.115-123
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• 2000

In this paper, a block FIR(Finite Impulse Response) filtering architecture is proposed for IF digital down converter. Digital down converter consists of digital mixers. decimation filters and down samplers. In this proposed structure, it is shown that a efficient parallel decimation filter architecture can be produced by cancellation of inherent up sampling of the block filter and following down sampler Furthermore. it is shown that computational complexity of the proposed architecture is reduced by exploiting the block FIR structure and zero values of the digital mixers.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.273-276
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• 2003

In this paper, we designed and made up/down converter (UDC) for using W-CDMA digital pre-distortion system which is one of the efficiency enhancement techniques. UDC is required that frequency up(baseband to RF) and down(RF to baseband) of information signals. The focus of the design and PCB layout is to satisfy the linearity of the UDC. We tested that UDC was satisfied specification which is based on 3GPP base stations and repeaters. The ACLR results which are -51.84dBc(Up Converter) and -55.0dBc(Down Converter) at upper 5 MHz offset from center-frequency show that UDC satisfy the 3GPP specification with superior linearity data.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.264-271
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• 2011

ILS(Instrument Landing System) is the international standard system for approach and landing guidance. ILS was adopted by ICAO(International Civil Aviation Organization) in 1947 and is currently being used in commercial systems. To design the digital transmitter and receiver modules that can be mounted in the integrated ILS, we propose the digital design methods of digital double AM modulator and demodulator using FPGA chip, DDS(Direct Digital Synthesizer) for generation of sampling clock, demodulator of DDC(Digital Down Converter) structure, and spectrum analyzer using DSP chip. We demonstrate the efficiency of the proposed design method through experiments using developed transmitter and receiver modules. This system can be used as a high-performance commercial system.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2589-2591
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• 2002

송수신기의 방식에는 직접변환 방식과 기저대역 신호와 LO(Local Oscillator)를 혼합하여 interpolation 기법을 사용하여 중간 주파수 단계까지 up conversion을 하고 두 번째 LO와 IF신호를 혼합하여 RF신호로 변환하여 송신하는 헤테로다인 방식이 존재한다. 본 논문에서는 이런 송수신기 방식 중에서 헤테로다인 방식을 적용하여 QPSK에서의 digital up /down converter를 Simulink 환경에서 설계 및 구현하였다. Up converter는 4배의 interpolation 필터와 4단짜리 cascaded integrate-comb(CIC)필터를 사용하여 입력데이터의 샘플 레이트를 클럭 레이트까지 증가시켰으며, numerically controlled oscillator (NCO)와 mixer를 사용하여 신호를 변조하였다. Down converter의 구조는 up converter와 동일하며 단지 up converter의 반대순서로 구성되어있다. 이런 모든 과정을 Simulink를 이용한 시뮬레이션과 스펙트럼 분석기를 사용하여 검증해 보았다.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.115-120
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• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.5
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• pp.336-342
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• 2017

Recently, there has been an increasing need for underwater communication systems to monitor ocean environments and prevent marine disasters, as well as to secure ocean resources. Most underwater communication systems adopted acoustic communication with a consideration of attenuation, absorption, and scattering in conductive sea water, and developed fully digital modems based on processors. In this study, a digital up converter (DUC) and a digital down converter (DDC) was developed for an underwater basestation based on underwater acoustic communication systems. Because one of the most important issues in underwater acoustic communication systems is low power consumption due to environmental problems, this study developed a specific hardware module for DUC and DDC. It supported four links of underwater acoustic communication systems and converted the sampling rate and frequency. The systemwas designed and verified using Verilog-HDL in ModelSim environment with the test data generated from baseband layer parts for an underwater base station.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.961-965
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• 2006

Design Up/Down converters which use Digital IF( Intermediate Frequency) techniques from the present paper, against hereupon performance the criticism. The reason which uses Digital IF techniques is configured of passive elements and the position If frequency domains are fixed and they do not use in the position one frequency but, the external fringe land of the board which comes to be configured with Digital IF without from the communication frequency domain which is various there to be a flexibility, the use was under possibility. Like this configuration compares in analog Heterodyne mode of existing and it has the performance upgrade which is excellent it shows a high flexibility.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.3
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• pp.43-50
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• 2010

DDC(Digital Down Converter) is a conversion technology to decimate to a lower sampling rate and DDC for the future development of communications technology has the necessary skills. So, it has been recognized in the wireless and the SDR(Software Defined Radio) system as essential components. In addition, research is underway on spectrum sensing for efficient communications environment due to the shortage of frequency resources. In this paper, the DDC systems were analyzed for CIC(Cascaded Integrator Comb) Filter, WDF(Wave Digital Filter), SRC(Sample Rate Conversion) each module. Moreover, we proposed a linkage effectively between DDC system and Spectrum Sensing for improve the efficiency of use of frequency by computer simulations. The simulation results of the DDC system was applied to the spectrum sensing capabilities. Also, performance and complexity of the results were derived and proposed system was the result of the check.