• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.23 no.6
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• pp.539-546
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• 2014

This paper describes an ultra-precision electronic clinometer, which is based on the capacitive-based fluid type, for detection of small inclination angles. The main parts of the clinometer low-noise electronics are two capacitance measurement circuits for converting the capacitances of the capacitors of the clinometer into voltages, and a differential amplifier for obtaining the difference of the capacitances, which is proportional to the input inclination angle. A 16 bit analog to digital (AD) converter is also embedded into the same circuit board, whose output is sent to a PC via RS-232C, for achieving a small noise level down to tens of ${\mu}v$. A compensation method, which is referred to as the delay time method for shortening the stabilization time of the sensor was also discussed. Experimental results have shown the possibility of achieving a measurement resolution of $0.0001^{\circ}$ as well as the quick measurement with the delay time method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.22-28
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• 2009

This paper presents a fast received signal strength indicator (RSSI) circuit for wireless communication application. The proposed circuit is developed using power detectors and an analog-to-digital converter to achieve a fast settling time. The power detector is consisted of a novel logarithmic variable gain amplifier (VGA), a peak detector, and a comparator in a closed loop. The VGA achieved a wide logarithmic gain range in a closed loop form for stable operation. For the peak detector, a fast settling time and small ripple are obtained using the orthogonal characteristics of quadrature signals. In $0.18-{\mu}m$ CMOS process, the RSSI value settles down in $20{\mu}s$ with power consumption of 20 mW, and the maximum ripple of the RSSI is 30 mV. The proposed RSSI circuit is fabricated with a personal handy-phone system transceiver. The active area is $0.8{\times}0.2\;mm^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.307-310
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• 2001

In this paper we describe the design and implementation of uplink receiver for BWLL base station modem. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we use Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.1

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.258-264
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• 2015

The first 77 GHz transceiver that applies a heterodyne structure-based linear frequency modulation-frequency shift keying (LFM-FSK) front-end module (FEM) is presented. An LFM-FSK waveform generator is proposed for the transceiver design to avoid ghost target detection in a multi-target environment. This FEM consists of three parts: a frequency synthesizer, a 77 GHz up/down converter, and a baseband block. The purpose of the FEM is to make an appropriate beat frequency, which will be the key to solving problems in the digital signal processor (DSP). This paper mainly focuses on the most challenging tasks, including generating and conveying the correct transmission waveform in the 77 GHz frequency band to the DSP. A synthesizer test confirmed that the developed module for the signal generator of the LFM-FSK can produce an adequate transmission signal. Additionally, a loop back test confirmed that the output frequency of this module works well. This development will contribute to future progress in integrating a radar module for multi-target detection. By using the LFM-FSK waveform method, this radar transceiver is expected to provide multi-target detection, in contrast to the existing method.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.14-23
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• 2010

This paper reports the fabrication of a DVB-T/H System in Package (SiP) that is able to receive and process the DVB-T/H signal. The DVB-T/H is the European telecommunication standard for Digital Video Broadcasting (DVB). An IC-embedded Printed Circuit Board (PCB) process, interpose a chip between PCB layers, has applied to the DVB-T/H SiP. The chip inserted in DVB-T/H SiP is the System on Chip (SoC) for mobile TV. It is comprised of a RF block for DVB-T/H RF signal and a digital block to convert received signal to digital signal for an application processor. To operate the DVB-T/H IC, a 3MHz DC-DC converter and LDO are on the DVB-T/H SiP. And a 38.4MHz crystal is used as a clock source. The fabricated DVB-T/H SiP form 4 layers which size is $8mm{\times}8mm$. The DVB-T/H IC is located between 2nd and 3rd layer. According to the result of simulation, the RF signal sensitivity is improved since the layout modification of the ground plane and via. And we confirmed the adjustment of LC value on power transmission is necessary to turn down the noise level in a SiP. Although the size of a DVB-T/H SiP is decreased over 70% than reference module, the power consumption and efficiency is on a par with reference module. The average power consumption is 297mW and the efficiency is 87%. But, the RF signal sensitivity is declined by average 3.8dB. This is caused by the decrease of the RF signal sensitivity which is 2.8dB, because of the noise from the DC-DC converter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.2C
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• pp.209-216
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• 2009

The repeater for wireless broadband internet (Wibro) system using OFDM demands the short processing delay to eliminate inter-symbol interference resulted from the time delay greater than the guard time. Towards this, the total system delay of repeater is expected to be minimized as possible as it can without distorting signal quality. In general, the FIR-type of filter is commonly deployed as a channelization filter, but due to its large amount of coefficients for producing prerequisite filter response the excessive large time delay occurs. To withstand this problem, the paper proposes the method for designing IIR filter whose response almost identical to that of the original filter. Moreover, in order to linearize the phase response of the designed IIR filter, this paper also introduce the way of designing the all-pass filter to be cascaded works for linearizing phase response of the channelization as well as the de-channelization filter. To achieve the further improvement in linearization of the phase response and reduction of the overall complexity, this paper tries to transform the integrated IIR filter group into the structure in polyphase style. The computer simulation verifies that the integrated IIR filter group designed in this paper reveals the relatively short processing delay without harming the acceptible signal quality.

• Journal of IKEEE
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• v.16 no.1
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• pp.28-33
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• 2012

Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

• Journal of Power Electronics
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• v.16 no.2
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• pp.464-472
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• 2016

This study applies the selective harmonic elimination (SHE) technique to design and operate a regulated AC/DC/AC power supply suitable for maritime military applications and underground trains. The input is a single 50/60 Hz AC voltage, and the output is a 400 Hz regulated voltage. The switching angles for a multi-level inverter and transformer turns ratio are determined to operate with special connected transformers with equal power ratings and produce an almost sinusoidal current. As a result of its capability of directly controlling harmonics, the SHE technique is applicable to apparatus with congenital immunity to specific harmonics, such as series-connected transformers, which are specially designed to equally share the total load power. In the present work, a single-phase 50/60 Hz input source is rectified via a semi-controlled bridge rectifier to control DC voltage levels and thereby regulate the output load voltage at a constant level. The DC-rectified voltage then supplies six single-phase quazi-square H-bridge inverters, each of which supplies the primary of a single-phase transformer. The secondaries of the six transformers are connected in series. Through off-line calculation, the switching angles of the six inverters and the turns ratios of the six transformers are designed to ensure equal power distribution for the transformers. The SHE technique is also employed to eliminate the higher-order harmonics of the output voltage. A digital implementation is carried out to determine the switching angles. Theoretical results are demonstrated, and a scaled-down experimental 600 VA prototype is built to verify the validity of the proposed system.