• 문화기술의 융합
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• 제6권3호
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• pp.427-430
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• 2020

IoT 분야와 의료 측정기기 분야에서 여러 개의 아날로그 입력 신호를 동시에 디지털 신호로 변환하는 기술 요구가 늘어나고 있다. 기존 단일 또는 2개의 체널 방식을 이용하여 여러 개의 아날로그 신호를 처리하는 방식에서는 하드웨어 크기와 전력소모 면에서 응용 제한을 받게 된다. 본 논문에서는 여러 개의 아날로그 입력을 동시에 받아서, 각각에 대한 24비트 디지털 신호를 출력하는 다채널 24비트 ADC 용 콤필터 설계 및 구현을 기술하였다. 제안된 콤필터의 기능은 매트랩 시뮬레이션과 FPGA 테스트 보드로 검증하였다. SK 하이닉스 0,35㎛ CMOS 표준 공정을 이용하여 칩으로 제작하였다. 미분기/적분기 사용 또는 FIR 구조의 기존 방식과 성능, 칩 면적을 비교하였다. 제안된 콤필터는 6개 이상의 다채널 아날로그 입력, 저 전력 소모, 작은 하드웨어 크기를 요구하는 IoT 제품과 의료 측정기기 활용이 예상된다.

• 대한전자공학회논문지
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• 제19권3호
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• pp.5-12
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• 1982

기본 모음의 분석을 위한 특징 파라미터로 특정 대역의 에너지의 비를 이용하는 방법을 사용하여 이 파라미터와 영통과률(zero crossing rate;ZCR) 그리고 에너지 파라미터의 논리 조합으로 한국어 기본산자 음성의 인식을 시도하였다. 본 실험을 위해서 음성 신호는 차단 주파수 10KHz의 저역 여파기로 여파되었고 20KHz의 표본화율로 표본화 되어 IBM 370으로 시뮬레이션 되었다. 본 시뮬레이션에서는 리메쯔 교환 알고리즘[l3].[14]에 의해 61차, 120차, 25차, 25차 등 4개의 FIR 디지탈 여파기를 설계하여 사용하였다. 실험 결과 3인의 화자에 대해서 92%의 인식률을 얻었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.109-116
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• 2014

This paper presents a high-efficiency digital class-D audio amplifier using a composite interpolation filter for portable audio devices. The proposed audio amplifier is composed of an interpolation filter, a delta-sigma modulator, and a class-D output stage. To reduce power consumption, the designed interpolation filter has an optimized composite structure that uses a direct-form symmetric and Lagrange FIR filters. Compared to the filters with homogeneous structures, the hardware cost and complexity are reduced by about half by the optimization. The coefficients of the digital delta-sigma modulator are also optimized for low power consumption. The class-D output stage has gate driver circuits to reduce shoot-through current. The implemented class-D audio amplifier exhibited a high efficiency of 87.8 % with an output power of 57 mW at a load impedance of $16{\Omega}$ and a power supply voltage of 1.8 V. An outstanding signal-to-noise ratio of 90 dB and a total harmonic distortion plus noise of 0.03 % are achieved for a single-tone input signal with a frequency of 1 kHz.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.425-435
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• 2016

This paper describes a spread-spectrum clock generation method by utilizing a ${\Delta}{\Sigma}$ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order ${\Delta}{\Sigma}$ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The ${\Delta}{\Sigma}$ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 GHz spread-spectrum clock generator (SSCG) is implemented in 65 nm CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 dB and 11 dB with 10 kHz and 100 kHz resolution bandwidths respectively, consuming 6.34 mW from a 1 V supply.

• 음성과학
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• 제9권3호
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• pp.17-24
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• 2002

The goal of this research is the real-time implementation of an AEC (Acoustic Echo Canceller) using the floating-point digital signal processor of TMS320C31. We employ an FIR-type adaptive filter with the conventional NLMS (Normalized Least Mean Square) algorithm for the adaptation of filter coefficients. We program and optimize the system in the assembler level to make it run in real-time. With 8 kHz sampling rate, the implemented AEC requires $46\;\mu$sec and $77\;\mu$sec computational time per sample for 128-and 256-tap filter, respectively. It corresponds to 37% and 62% of maximum computational ability of TMS320C31 DSP.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.193-199
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• 2008

A combined clock and data recovery (CDR) circuit with adaptive cancellation of data-dependent jitter (DDJ) is constructed in all-digital architecture which is amenable to deep submicron technology. The DDJ canceller uses an adaptive FIR filter to compen-sate for any unknown channel characteristic. The proposed CDR decreases jitter in the recovered clock since the DDJ canceller significantly cancels out incoming jitter caused by inter-symbol interference.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.443-450
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• 2013

This paper propose a new ROM data encoding method that takes into account of a sequential access pattern to reduce the power consumption in ROMs used in applications such as FIR filters that access the ROM sequentially. In the proposed encoding method, the number of 1's, of which the increment leads to the increase of the power consumption, is reduced by applying an exclusive-or (XOR) operation to a bit pair composed of two consecutive bits in a bit line. The encoded data can be decoded by using XOR gates and D flip-flops, which are usually used in digital systems for synchronization and glitch suppression. By applying the proposed encoding method to coefficient ROMs of FIR filters designed by using various design methods, we can achieve average reduction of 43.7% over the unencoded original data in the power consumption, which is larger reduction than those achieved by previous methods.

• 한국음향학회지
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• 제6권3호
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• pp.52-59
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• 1987

본 논문에서 선형 델타 변조방식을 간단한 아날로그/디지탈 변환기로 이용하여 무한 응답 디지탈 여파기를 구현하는 방법을 제시하였다. 이 방법은 하드웨어 승산기나 펄스 부호변환 아날로그/디지탈 변환기를 필요로 하지 않으므로 종래의 무한응답 디지탈 여파기의 구현방법보다 매우 간단하다. Lee와 Un의 유한응답LDMDF에 비해서 이 무한응답LDMDF는 매우 적은 계산시간이 요구된다.

• 한국통신학회논문지
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• 제22권2호
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• pp.306-317
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• 1997

This ppaer presents a bit-rate conversion system for efficient communications between 3 channel CVSD systems with different bit-rates. The proposed conversion system is implemented in the digital domain and specially, the conversion problem between 32 Kbps and 16 Kbps CVSD systems is studied. The conventional conversion system implemented in the analog domain allows signals to be easily degraded by external noises. To overcome this problem, a digital CVSD bit-rate conversion system robust to external noises is developed. the new systemdecodes CVSD bit sequences and converts sampling rates of decoded signals, then encodes signals at target bit-rates. Since linear phase property does not matter in this application, instead of FIR filters a IIR filter is employed to reduce the system complexity. Therefore, a 3 channel digital CVSD bit-rate conversion system was successfully real-time implemented using a general purpose DSP. In addition, conversion problems with unkown time constants were experimented and good experimental results were obtained.

• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.192-200
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• 2018

In this study, improvements for error correction, speed, position, and rotation calculation algorithms have been proposed to be used in resolver to digital conversion (RDC) systems. The proposed open-loop system drives the resolver and uses the output signals of the resolver signal to estimate the real time position, the instant speed, and the rotation count with high resolution and accuracy even at high speeds and noise. The proposed solution implements strong features of both closed and open loop based systems while eliminating their weak points. The improvements proposed is resistant to noise owing to digital FIR filter and data averaging techniques. The implementation used for proof of concept is implemented on a hardware using an FPGA and configurable to be used by any resolver.