• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.429-429
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• 2010

TFT 제조 방법 중 LTPS (Low Temperature Polycrystalline Silicon)는 저온과 저비용 등의 이점으로 인하여 flat panel display 제작에 널리 사용된다. 이동도와 전류 점멸비 등에서 이점을 가지는 ELA(Excimer Laser Annealing)가 널리 사용되고 있지만, 이 방법은 uniformity 등의 문제점을 가지고 있다. 이를 극복하기 위한 방법으로 MICC(Metal Induced Capping Crystallization)이 사용되고 있다. 이 방법은 $SiN_x$, $SiO_2$, SiON등의 capping layer를 diffusion barrier로 위치시키고, Ni 등의 금속을 capping layer에 도핑 한 뒤, 다시 한번 열처리를 통하여 a-Si에 Ni을 확산시키킨다. a-Si 층에 도달한 Ni들이 seed로 작용하여 Grain size가 매우 큰 film을 제작할 수 있다. 채널의 grain size가 클 경우 grain boundary에 의한 캐리어 scattering을 줄일 수 있기 때문에 MIC 방법을 사용하였음에도 ELA에 버금가는 소자의 성능과 안정성을 얻을 수있었다. 본 연구에서는 large grain TFT의 Gate bias stress에 따른 소자의 안정성 측정 및 분석에 목표를 두었다.

• Journal of the Korean Society for Heat Treatment
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• v.4 no.2
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• pp.1-8
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• 1991

The spheroidization of cold rolled lamellar pearlite in annealing at the temperatures between 600 and $700^{\circ}C$ has been studied by quantitative micrography. It was foud that the spheroidization proceeded as two stageh. The first stage was the stage of relieving the stored energy by cold work, the second was the stage of reducing the interface energy between ferrite and cementite. The spheroidization rate combining the spheroidization rate of each stages is described by the following equation : $$d(1/S)/dt=k_3{\cdot}D/_{(1/s)}\{{\sigma}V/_{(1/s)}+k_4{\cdot}{\exp}(-bt)\}$$ Where, S is the total area of the interface between ferrite and cementite per unit volume, D is the diffusion coefficient, ${\sigma}$ is the boundary energy, V is the volume fraction of the cementite, and $k_3$, $k_4$, b are constants.

• Proceedings of the Optical Society of Korea Conference
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• 1989.02a
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• pp.172-175
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• 1989

1.3${\mu}{\textrm}{m}$ surface-emitting GaInAsP/InP LED was fabricated by two-phase supercooling LPE technique. The lattice mismatch of the grown DH wafer was typically 0.03%. The processes involve SiO2 CVD, lithography, Zn diffusion, lift-off, lapping, annealing, and wire bonding. The fabricated LED shows the optical power of 600㎼ at 70mA driving current, differential resistance of 4$\Omega$, the f3dB of 35MHz, and the FWHM of 1040{{{{ ANGSTROM }}. The peak wavelength of the fabricated LED was at 1.29${\mu}{\textrm}{m}$(100mA).

• Korean Journal of Materials Research
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• v.20 no.12
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• pp.661-668
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• 2010

Cu(In,Ga)$Se_2$(CIGS) photovoltaic thin films were electrodeposited on Mo/glass substrates with an aqueous solution containing 2 mM $CuCl_2$, 8 mM $InCl_3$, 20 mM $GaCl_3$ and 8mM $H_2SeO_3$ at the electrodeposition potential of -0.6 to -1.0 V(SCE) and pH of 1.8. The best chemical composition of $Cu_{1.05}In_{0.8}Ga_{0.13}Se_2$ was found to be achieved at -0.7 V(SCE). The precursor Cu-In-Ga-Se films were annealed for crystallization to chalcopyrite structure at temperatures of 100-$500^{\circ}C$ under Ar gas atmosphere. The chemical compositions, microstructures, surface morphologies, and crystallographic structures of the annealed films were analyzed by EPMA, FE-SEM, AFM, and XRD, respectively. The precursor Cu-In-Ga-Se grains were grown sparsely on the Mo-back contact and also had very rough surfaces. However, after annealing treatment beginning at $200^{\circ}C$, the empty spaces between grains were removed and the grains showed well developed columnar shapes with smooth surfaces. The precursor Cu-In-Ga-Se films were also annealed at the temperature of $500^{\circ}C$ for 60 min under Se gas atmosphere to suppress the Se volatilization. The Se amount on the CIGS film after selenization annealing increased above the Se amount of the electrodeposited state and the $MoSe_2$ phase occurred, resulting from the diffusion of Se through the CIGS film and interaction with Mo back electrode. However, the selenization-annealed films showed higher crystallinity values than did the films annealed under Ar atmosphere with a chemical composition closer to that of the electrodeposited state.

• Korean Journal of Materials Research
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• v.7 no.1
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• pp.69-75
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• 1997

Thin films of $Si0_2(1000{\AA})/CoNiCr(400{\AA})/Cr$ were fabricated as a function of Cr thickness by KF magnetron sputtering. The saturation magnetization, coercive force and squareness with annealing temperature for these films were investigated. The values of saturation magnetization of $SiO_2/CoNiCr/Cr$ thin films decreased as the thickness of Cr underlayer increased, whereas coercive force increased as the thickness of Cr underlayer increased. The value of Ms was 600 emu/cc and the maximum value of Hc was 550 Oe. Especially, the value of saturation magnetization was rapidly decreased $SiO_2/CoNiCr/Cr(1700{\AA})$ thin films as the annealing temperature increased And the coercive force increased as the annealing temperature increased When annealing temperature was $650^{\circ}C$, the Ms was reduced to 90 % of the as-deposited film. And the Hc was showed maximum 1600 Oe. It was thought that Cr diffusion into CoNiCr layer reduced the magnetic moment of CoKiCr layer. In addition. Hc might he increased due to grain growth perpendicular to the film plane.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

• Journal of the Korean Vacuum Society
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• v.5 no.3
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• pp.258-262
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• 1996

We have investigated the changes in magnetoresistive characteristics, interfacial roughness, and preferred orientation with the Fe buffer layer thickness, annealing temperature, and the stacking number of layers variation in Fe/[NiFe/Cu] multilayers by using the 3-gun d.c. magnetron sputtering method. Intensity of the (200) orientation was increased with the increment of the Fe-buffer layer thickness. We found a maximum magnetoresistance ration of 4.7%, when the buffer layer thickness was 70$\AA$, and the field sensitivity also showed a maximum value at the same thickness. We varied the stacking number of multilayers with fixing the Fe buffer layer thickness of 70$\AA$. When the stacking number was 40 layers, maximum MR ratio(5.3%) was observed. With the variation of annealing temperature no change in the MR ratio was found beyond $300^{\circ}C$. But decrement of MR ratio was observed above $300^{\circ}C$. This decrement of the MR ratio was responsible for the increment of paramagnetic mixed layer caused by the diffusion of Cu layer and the change of antiferromagnetic coupling.

• Journal of the Korean Vacuum Society
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• v.11 no.4
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• pp.207-211
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• 2002

Band gap tuning by quantum well disordering in $In_{0.53}Ga_{0.47}As/InGaAsP(Q1.25)$ quantum well structure has been investigated using photoluminescence. The threshold temperature for the blue shift was about $750^{\circ}C$ , and the blue shift became larger as the annealing temperature increased. $SiO_2$ showed saturation as the annealing temperature increased. $SiN_x$caused larger blue shift than $SiO_2$, which is considered to be related to the low growth temperature of $SiN_x$. The diffusion of P and Ga are thought to be responsible for the blue shift of the $SiN_x$ and $SiO_2$capped quantum well disordering , respectively.

• Korean Journal of Materials Research
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• v.8 no.7
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• pp.579-583
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• 1998

Silicide layer structures, agglomeration of silicide layers, and dopant redistributions for the Co/Ti bilayer sputter-deposited on the P-doped polycrystalline Si substrate and subjected to rapid thermal annealing were investigated and compared with those on the single Si substrate. The $CoSi_2$ phase transition temperature is higher and agglomeration of the silicide layer occurs more severely for the Co/Ti bilayer on the doped polycrystalline Si substrate than on the single Si substrate. Also, dopant loss by outdiffusion is much more significant on the doped polycrystalline Si substrate than on the single Si substrate. All of these differences are attributed to the grain boundary diffusion and heavier doping concentration in the polycrystalline Si. The layer structure after silicidation annealing of Co/ Tildoped - polycrystalline Si is polycrystalline CoSi,/polycrystalline Si, while that of Co/TiI( 100) Si is Co- Ti- Si/epi- CoSi,/(lOO) Si.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.80-90
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• 1994

To develop VLSI of higher packing density with 0.5.mu.m gate length of less, semiconductor devices require shallow junction with higher doping concentration. the most common method to form the shallow junction is ion implantation, but in order to remove the implantation induced defect and activate the implanted impurities electrically, ion-implanted Si should be annealed at high temperature. In this annealing, impurities are diffused out and redistributed, creating deep PN junction. These make it more difficult to form the shallow junction. Accordingly, to miimize impurity redistribution, the thermal-budget should be kept minimum, that is. RTA needs to be used. This paper reports results of the diffusion characteristics of PSG film by varying Phosphorus weitht %/ Times and temperatures of RTA. From the SIMS.ASR.4-point probe analysis, it was found that low sheet resistance below 100 .OMEGA./ㅁand shallow junction depths below 0.2.mu.m can be obtained and the surface concentrations are measured by SIMS analysis was shown to range from 2.5*10$^{17}$ aroms/cm$^{3}$~3*10$^{20}$ aroms/cm$^{3}$. By depending on the RTA process of PSG film on Si, LDD-structured nMOSFET was fabricated. The junction depths andthe concentration of n-region were about 0.06.mu.m. 2.5*10$^{17}$ atom/cm$^{-3}$ , 4*10$^{17}$ atoms/cm$^{-3}$ and 8*10$^{17}$ atoms/cm$^{3}$, respectively. As for the electrical characteristics of nMOS with phosphorus junction for n- region formed by RTA, it was found that the characteristics of device were improved. It was shown that the results were mainly due to the reduction of electric field which decreases hot carriers.