• Journal of the Optical Society of Korea
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• v.11 no.4
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• pp.153-157
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• 2007

We have proposed an application of disturbance observer with PID controller to minimize gain-transient time of wavelength-division-multiplexing(WDM) multi channels in optical amplifier in channel add/drop networks. We have dramatically reduced the gain-transient time to less than $3{\mu}sec$ by applying a disturbance observer with a proportional/integral/ differential(PID) controller to the control of amplifier gain. The theoretical analysis on the 3-level erbium-doped fiber laser and the disturbance observer technique is demonstrated by performing the simulation with co-simulation of the $MATLAB^{TM}$ and a numerical modeling software package such as the $Optsim^{TM}$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.143-149
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• 2008

A novel compact model for a five-port transformer balun is proposed for the efficient circuit design of hybrid balun. Compared to the conventional model, the proposed model provides much faster computation time and more reasonable values for the extracted parameters. The hybrid balun, realized in $0.18\;{\mu}m$ CMOS, achieves 2.8 dB higher gain and 1.9 dB lower noise figure than its passive counterpart only at a current consumption of 0.67 mA from 1.2 V supply. By employing the hybrid balun, a differential zero-IF receiver is designed in $0.18\;{\mu}m$ CMOS for IEEE 802.15.4 ZigBee applications. It is composed of a differential cascode LNA, passive mixers, and active RC filters. Comparative investigations on the three receiver designs, each employing the hybrid balun, a simple transformer balun, and an ideal balun, clearly demonstrate the advantages of the hybrid balun in fully differential CMOS RF receivers. The simulated results of the receiver with the hybrid balun show 33 dB of conversion gain, 4.2 dB of noise figure with 20 kHz of 1/f noise corner frequency, and -17.5 dBm of IIP3 at a current consumption of 5 mA from 1.8 V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.31-37
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• 2009

This paper presents an efficient frame synchronization strategy with the identification of modulation type for Digital Video Broadcasting-Satellite second generation (DVB-S2). To detect the Start Of Frame (SOF) and identify a modulation mode at low SNR, we propose a new correlator structure and a low complexity Automatic Gain Controller (AGC). The proposed frame synchronization architecture can reduce about 93% multipliers and 89% adders compared with the direct implementation of the Differential - Generalized Post Detection Integration (D-GPDI) algorithm which is very complex and the proposed a low complexity AGC consists of only 5 multipliers and 3 adders. The proposed architecture has been thoroughly verified on the Xilinx Virtex II FPGA board.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.281-288
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• 2004

In this paper, we consider the diversity combining method for multiple symbol differential detection (MSDD) over the slow fading diversity channel. Though the performance of the optimum maximum-likelihood sequence estimator for MSDD approaches the performance of maximal-ratio combining with differential encoding, the complexity increases exponentially as the size of MSDD block is increased. This new pre-combining method can make use of the efficient MSDD algorithm that has a complexity increasing linearly with the block length or MSDD. Thus, in many wireless scenarios where it is not possible to perform coherent detection. this pre-combined diversity MSDD can be applied to obtain substantial gain compare to conventional differential detection.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.276-281
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• 2005

This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth, $0{\sim}20\;dB$ gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential $0.2{\sim}2.5Vpp$ input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is $44{\sim}46MHz$, sampling freq. is 25MHz), we can process the IF QPSK signal ($44{\sim}46MHz$) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.

• Transactions on Electrical and Electronic Materials
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• v.2 no.4
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• pp.1-6
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• 2001

In this paper, a 1.5 V high-gain high-frequency CMOS complementary operational amplifier is presented. The input stage of op-amp is designed for supporting the constant transconductance on the Input stage by consisting of the parallel-connected rail-to-rail complementary differential pairs. And consisting of the class-AB rail-to-rail output stage using the concept of elementary shunt stage and the grounded-gate cascode compensation technique for improving the low PSRR which was a disadvantage in the general CMOS complementary input stage, the load dependence of open loop gain and the stability of op- amp on the output load are improved, and the high-gain high-frequency operation can be achieved. The designed op-amp operates perfectly on the complementary mode with the 180° phase conversion for a 1.5 V supply voltage, and shows the DC open loop gain of 84 dB, the phase margin of 65°, and the unity gain frequency of 20 MHz. In addition, the amplifier shows the 0.1 % settling time of .179 ㎲ for the positive step and 0.154 ㎲ for the negative step on the 100 mV small-signal step, respectively, and shows the total power dissipation of 8.93 mW.

• Journal of Korea Society of Digital Industry and Information Management
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• v.20 no.2
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• pp.63-74
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• 2024

This Paper presents a resistive wideband fully differential low-noise amplifier (LNA) designed using a noise-cancellation technique for TV tuner applications. The front-end of the LNA employs a cascode common-gate (CG) configuration, and cross-coupled local feedback is employed between the CG and common-source (CS) stages. The moderate gain at the source of the cascode transistor in the CS stage is utilized to boost the transconductance of the cascode CG stage. This produces higher gain and lower noise figure (NF) than a conventional LNA with inductor. The NF can be further optimized by adjusting the local open-loop gain, thereby distributing the power consumption among the transistors and resistors. Finally, an optimized DC gain is obtained by designing the output resistive network. The proposed LNA, designed in SK Hynix 180 nm CMOS, exhibits improved linearity with a voltage gain of 10.7 dB, and minimum NF of 1.6-1.9 dB over a signal bandwidth of 40 MHz to 1 GHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7A
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• pp.731-742
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• 2010

We propose an incremental relaying protocol in conjunction with opportunistic communication for differential modulation with an aim to make efficient use of the degrees of freedom of the channels by exploiting a imited feedback signal from the destination. In particular, whenever the direct link from the source to the destination is not favorable to decoding, the destination will request the help from the opportunistic relay (if any). The performance of the proposed system is derived in terms of average bit error probability and achievable spectral efficiency. The analytic results show that the system assisted by the opportunistic relaying can achieve full diversity at low SNR regime and exhibits a 30㏈ gain relative to direct transmission, assuming single-antenna terminals. We also determine the effect of power allocation on the bit error probability BEP) performance of our relaying scheme. We conclude with a discussion on the relationship between the given thresholds and channel resource savings. Monte-Carlo simulations are performed to verify the analysis.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.7
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• pp.23-29
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• 1997

The performance degradation of CMOS differential amplifiers due to hot carrier effect has been measured and analyzed. Two-state CMOS amplifiers whose input transistors are PMOSFETs were designed and fabriacted using the ISRC CMOS 1.5.mu.m process. It was observed after the amplifier was hot-carrier stressed that the small-signal voltage gain and the input offset voltage increased and the phase margin decreased. The performance variation results from the increase of the transconductances and gate capacitances of the PMOSFETs used as input transistors in the differential input stage and the output stage and also resulted from the decrease of their output conductances. After long-term stress, the amplifier became unstable. The reason might be that its phase margin was reduced due to hot carrier effect.

• Journal of electromagnetic engineering and science
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• v.6 no.1
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• pp.18-23
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• 2006

In this paper, we demonstrate a fully integrated X-band image rejection down converter, which was developed using InGaP/GaAs HBT MMIC technology, consists of two single-balanced mixers, a differential buffer amplifier, a differential YCO, an LO quadratue generator, a three-stage polyphase filter, and a differential intermediate frequency(IF) amplifier. The X-band image rejection downconverter yields an image rejection ratio of over 25 dB, a conversion gain of over 2.5 dB, and an output-referred 1-dB compression power$(P_{1dB,OUT})$ of - 10 dBm. This downconverter achieves broadband image rejection characteristics over a frequency range of 1.1 GHz with a current consumption of 60 mA from a 3-V supply.