• 생물환경조절학회지
• /
• 제28권4호
• /
• pp.366-375
• /
• 2019

본 실험은 토마토(Solanum lycopersicum L. 'Hoyong' 'Super Doterang') 암면재배에서 배지 전체의 정전용량을 측정할 수 있는 장치(Substrate capacitance measurement device, SCMD)를 기반으로 한 적정 급액 방법을 구명하기 위하여 누적일사량 제어구(Integrated solar radiation automated irrigation, ISR)와 물관수액흐름 제어구(sap flow automated irrigation, SF)를 대조구로 비교하면서 봄부터 여름철과 겨울철에 재배를 실시하였다. SCMD 제어구는 급액 개시 후 배지 한 개당 설정된 배액 목표량이 처음 발생하는 시점까지 10분간격으로 급액하였고 첫 배액이 배출되면 그 때의 배지의 정전용량(Capacitance)을 100%로 간주하고 그 기준치의 급액제어점(Capacitance threshold, CT)에 도달하면 급액 되었고 그 뒤 목표 배액량이 발생하면 급액이 멈추는 방식으로 제어되었다. 봄부터 여름재배에서 실험 처리를 위해 SCMD제어구의 일회 급액량 (Irrigation volume per event)을 50, 75, 또는 100mL로 설정하였고 겨울철 재배에서는 CT가 0.65, 0.75, 또는 0.90가 되면 급액 되도록 설정하였다. 봄부터 여름철 재배에서 일회 급액량을 50, 75, 100mL로 설정하였을 때 급액 횟수는 각각 39, 29, 19회였고 배액율은 각각 3.04, 9.25, 20.18%였다. 겨울철 재배에서 CT를 0.65, 0.75, 0.90로 설정하였을 때 급액횟수는 각각 5.67, 6.50, 14.67회였고 배액율은 9.91, 10.78, 35.3%였다. 봄부터 여름철 재배에서 일회 급액량 처리에 따른 물관수액흐름속도(SF) 변화는 1회 급액량과 배액량을 각각 50과 75mL로 제한한 경우 100mL로 제한한 경우와 비교하여SF 신호가 외부 광량 신호 (SI) 보다 늦어지는 경향(time lag)을 보였고 겨울철 재배에서 CT를 0.65로 설정한 경우는 물관수액흐름 속도나 함수율이 매우 낮아졌고 CT를 0.90로 설정한 경우는 함수율과 물관수액흐름 속도는 매우 높았으나 많은 배액이 배출되었다. 따라서 토마토 봄부터 여름철 재배에서 SCMD를 활용하여 CT를 0.9로, 배지 한 개당 배액 목표량을 100mL로 설정하였을 때 일회 급액량은 75~100mL 범위가 적합하고 겨울철 재배에서는 1회 급액량을 75mL로, 배액 목표량을 70mL로 설정하였을 때 CT는 0.75이상 0.9이하 범위가 적합할 것으로 판단되었다. 앞으로 정전용량 값과 배지 용적수분함량의 관계성을 구명하고 보정계수를 구하는 연구가 필요할 것으로 판단된다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2009년도 하계학술대회 논문집
• /
• pp.131-131
• /
• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

• 센서학회지
• /
• 제30권6호
• /
• pp.436-440
• /
• 2021

The impact of the gate length (L_g) on the DC and high-frequency characteristics of indium-rich In_0.8Ga_0.2As channel high-electron mobility transistors (HEMTs) on a 3-inch InP substrate was inverstigated. HEMTs with a source-to-drain spacing (L_SD) of 0.8 ㎛ with different values of L_g ranging from 1 ㎛ to 19 nm were fabricated, and their DC and RF responses were measured and analyzed in detail. In addition, a T-shaped gate with a gate stem height as high as 200 nm was utilized to minimize the parasitic gate capacitance during device fabrication. The threshold voltage (V_T) roll-off behavior against L_g was observed clearly, and the maximum transconductance (g_{m_max}) improved as L_g scaled down to 19 nm. In particular, the device with an L_g of 19 nm with an L_SD of 0.8 mm exhibited an excellent combination of DC and RF characteristics, such as a g_{m_max} of 2.5 mS/㎛, On resistance (R_ON) of 261 Ω·㎛, current-gain cutoff frequency (f_T) of 738 GHz, and maximum oscillation frequency (f_max) of 492 GHz. The results indicate that the reduction of L_g to 19 nm improves the DC and RF characteristics of InGaAs HEMTs, and a possible increase in the parasitic capacitance component, associated with T-shap, remains negligible in the device architecture.

• ETRI Journal
• /
• 제26권6호
• /
• pp.583-588
• /
• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제12권3호
• /
• pp.278-285
• /
• 2012

A digital readout IC for capacitive sensors is presented. Digital capacitance readout circuits suffer from static capacitance of sensors, especially single-ended sensors, and require large passive elements to cancel such DC offset signal. For this reason, to maximize a dynamic range with a small die area, the proposed circuit features digital filters having a coarse and fine compensation steps. Moreover, by employing switched-capacitor circuit for the front-end, correlated double sampling (CDS) technique can be adopted to minimize low-frequency device noise. The proposed circuit targeted 8-kHz signal bandwidth and oversampling ratio (OSR) of 64, thus a $3^{rd}$-order ${\Delta}{\Sigma}$ modulator operating at 1 MH was used for pulse-density-modulated (PDM) output. The proposed IC was designed in a 0.18-${\mu}m$ CMOS mixed-mode process, and occupied $0.86{\times}1.33mm^2$. The measurement results shows suppressed DC power under about -30 dBFS with minimized device flicker noise.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 하계학술대회 논문집
• /
• pp.58-61
• /
• 2001

Metal-insulator-semiconductor (MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/cm$^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8V, 50% duty cycle) in the 500kHz.

• 전자공학회논문지A
• /
• 제29A권4호
• /
• pp.38-48
• /
• 1992

OEIC(Optoelectronic Integrated Circuit)'s can be integrated horizontally or vertically. Horizontal integration approach is, however, more immune to parasitic and more universally applicable. In this paper, a structural modeling, fabrication and characterization of PIN photodiodes which can be used in the horizontal integration are performed. For device modeling, we build a transmission line model from 2-D device simulation, from which lumped model parameters are extracted. The speed limits of the PIN photodiodes can also be calculated under various structural conditions from the model. Thus optimum design of horizontally integrated PIN photodiodes for high speed operation are possible. Such InGaAs/InP PIN photodiodes for long-wavelength communications are fabricated using pit etch, epi growth, planarization, diffusion and metallization processes. Planarization process using both RIE and wet etching and diffusion process using evaporated Zn$_{3}P_{2}$ film are developed. Characterization of the fabricated devices is performed through C-V and I-V measurements. At a reserve bias of 10V, the dark current is less than 5nA and capacitance is about 0.4pF. The calculated bandwidth using the measured series resistance and capacitance is about 4.23GHz.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
• /
• pp.407-407
• /
• 2008

무기EL 디스플레이는 고체재료에 전계를 가했을 때 발광하는 현상을 이용한소자로서, 급속도로 발전을 거듭하고 있으나, 유전체층에 강한전계를 가하여 발광하여야 하므로 낮은 Breakdown voltage와 효율의 한계로 인하여 휘도가 낮고 풀 컬러화 디스플레이 등 의 응용에는 적용되고 있지 못하는 실정이다. 본 연구에서는 강유전체 Perovskite 구조를 가지는 ABO3 물질 중 PMN(Lead Magnesium niobate) 과 PZT (Lead Zirconate titanate) 후막을 제조하여 Inorganic EL(Electro Luminance)에 적용하고 소자의 광전특성을 평가하였다. 소자에 사용된 기판은 고온소성에 알맞은 알루미나(Al2O3)기판을 채택 하였으며, 그 위 하부전극으로는 고온소성에 따른 화학적 안정성이 우수한 Au전극을 Screen Printing 하였다. 제조 되어진 PMN후막 페이스트는 PMN(Pb(Mg1/2 Nb2/3)O3) + Glass Frit(Pb-Zn-B) + BaTiO3(99.99%) 로 합성되었으며 하부전극위에 인쇄하였다. 그 다음 PZT sol-gel을 Spin coating으로 도포 하였다. 형광체로 ZnS:Cu.Cl 을 Screen Printing을로 형성하였으며, 평탄화를 위하여 유기물 충을 Screen Printing 공정으로 성막 하였다. 상부전극으로는 DC sputter로 ITO를 증착하여 EL소자 완성 후 Spectro - Chroma meter로 소자특성을 측정하였다. 평탄화를 통한 유기물층에 변화되는 Capacitance를 Oscilloscope로 전압 전류 pulse의 변화에 따른 opto-electronic 특성을 평가하였다.

• 한국수소및신에너지학회논문집
• /
• 제27권2호
• /
• pp.176-181
• /
• 2016

Recent years, supercapacitors have been attracting a growing attention as an efficient energy storage, due to their long-lifetime, device reliability, simple device structure and operation mechanism and, most importantly, high power density. Along with the increasing interest in flexible/stretchable electronics, the supercapacitors with compatible mechanical properties have been also required. A eutectic gallium-indium (EGaIn) liquid metal could be a strong candidate as a soft electrode material of the supercapacitors because of its insulating surface oxide layer for electric double layer formation. Here, we report the electrochemical study on the charging/reaction process at the interface of EGaIn liquid metal and electrolyte. Numerical fitting of the charging current curves provides the capacitance of EGaIn/insulating layer/electrolyte (${\sim}38F/m^2$). This value is two orders of magnitude higher than a capacitance of a general metal electrode/electrolyte interface.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
• /
• pp.438-439
• /
• 2006

We have used ITO/$Alq_3$/Al structure to study complex impedance in $Alq_3$ based organic light emitting diode. Equivalent circuit was analyzed in a device structure of ITO/$Alq_3$/Al by varying the thickness of $Alq_3$ layer from 60 to 400nm. The impedance results can be fitted using equivalent circuit model of parallel combination resistance $R_p$ and capacitance $C_p$ with a small series resistance $R_s$.