• Communications for Statistical Applications and Methods
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• v.5 no.2
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• pp.339-351
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• 1998

Designs for discriminating between two linear regression models are studied under $\Lambda$-type optimalities maximizing the measure for the lack of fit for the designs with fixed model inadequacy. The problem of selecting an appropriate $\Lambda$-type optimalities is shown to be closely related to the estimation method. $\Lambda$-type optimalities for the least squares and minimum bias estimation methods are considered. The minimum bias designs are suggested for the designs invariant with respect to the two estimation methods. First order minimum bias designs optimal under $\Lambda$-type optimalities are then derived. Finally for the case where the lack of fit test is significant, an approach to the construction of a second order design accommodating the optimal first order minimum bias design is illustrated.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.963-966
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• 1999

This Paper describes the design of high speed and low power comparator based on the feed forward bias control. Major building blocks of this comparator are composed of input offset canceling circuit and feed forward bias control circuit. The usual offset canceling circuit cancels the offset voltages by storing them in capacitors using MOS switches, The comparator of this paper employs the bias control circuit which generates bias signal from the input signal. The bias signal is applied to the capacitors and keeps the transfer of chares in the capacitors in the minimal amount, therefore making the comparator operate in stable condition and reduce decision time. The comparator in this form has very samll area and power dissipation. Maximum sampling rate is 200 Ms/sec. The comparator is designed in 0.65${\mu}{\textrm}{m}$ technology and the offset is less than 0.5㎷.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.393-396
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• 2001

In this paper, a new type of linearizer using a parallel diode with a bias feed resistance has been studied. It has positive gain and negative phase deviations because of a nonlinearity of the diode and movement of bias point cause by a voltage drop at the bias feed resistance. This predistortion linearizer consists of the little component and miniaturizes circuit design. The characteristics of this linearizer can be easily tuned using input bias voltage. In fabricated linearizer, maximum gain and Phase deviation of the linearizer is 1dB, 21$^{\circ}$ respectively. By applying its characteristics to the power amplifier, it will be linearized power amplifier.

• Journal of the Korean Society of Clothing and Textiles
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• v.42 no.4
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• pp.561-570
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• 2018

This study defined the changes of mechanical properties of silk fabric according to bias angles and investigated the influence of bias angles and fabric characteristics on hand value. For the experiments, 4 types of commercial silk plain weave fabrics were chosen. All fabrics had the same density, but different yarn characteristics. Fabric samples were cut into 12 different bias angles between $0^{\circ}$ and $165^{\circ}$ with $15^{\circ}$ gap and measured for tensile, shear, bending, surface properties by the KES-FB system. As a result, most mechanical parameters showed an asymmetry shape with $90^{\circ}$. The most flexible and easiest angles are $45^{\circ}$, $135^{\circ}$. Furthermore, the bias angles of silk fabrics were classified into three clusters with mechanical properties such as WT, 2HG, 2HG5, B, and SMD. The parameters according to fabric samples showed significant differences at WT, RT, B, 2HB, and MIU. It showed bigger effects as yarn fineness; in addition, twists were higher except RT. The results of hand value indicated that Koshi and Hari were highest with a bias angle of $75^{\circ}$; however, Shinayakasa was highest at bias angle of $45^{\circ}$. Finally, Shari was lowest at $45^{\circ}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.4
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• pp.384-393
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• 2013

In this paper, a design of planar microwave bias-tee using lumped elements was presented. The bias-tee is composed of 2 blocks; DC block and RF choke. For this design of the bias-tee, a wideband capacitor was used for DC block. For a RF choke, a series connection of inductors which have different SRFs is used for a RF choke. In the RF choke, a series connection of resistor and capacitor was added in shunt to eliminate a loss from a series resonance. The designed bias-tee was implemented by using 1608 SMT chip components. The fabricated bias-tee was measured using Anritsu 3680K fixture which enables to remove an effect of a connector. The fabricated bias-tee presented -15 dB of return loss and -1.5 dB insertion loss at 10 MHz~18 GHz.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.2
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• pp.104-110
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• 2008

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

• Journal of Positioning, Navigation, and Timing
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• v.1 no.1
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• pp.51-57
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• 2012

In this paper, design of an error model is presented in which the bias characteristic of the MEMS IMU is taken into consideration for performance enhancement of the MEMS IMU-based GPS/INS integrated navigation system. The drift bias of the MEMS IMU is modeled as a 1st-order Gauss-Markov (GM) process, and the autocorrelation function is obtained from the collected IMU data, and the correlation time is estimated from this. Prior to obtaining the autocorrelation function, the noise of IMU data is eliminated based on wavelet. As a result of simulation, it is represented that the parameters of error model can be estimated correctly only when a proper denoising is performed according to dynamic behavior of drift bias, and that the integrated navigation system based on error model, in which the drift bias is considered, provides more correct navigation performance compared to the integrated navigation system based on error model in which the drift bias is not considered.

• Journal of Microbiology and Biotechnology
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• v.15 no.6
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• pp.1377-1383
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• 2005

In a cDNA microarray experiment using Cy3 and Cy5 as labeling agents, particularly for the direct design, cDNAs from some genes incorporate one dye more efficiently than the other, which is referred to as the gene-specific dye bias. Dye-swaps, in which two dyes are switched on replicate arrays, are commonly used to control the gene-specific dye bias. We developed a simple procedure to extract the gene-specific dye bias information from a partial dye swap experiment. We detected gene-specific dye bias by identifying outliers in an X-Y plane, where the X axis represents the average log-ratio from two sets of dye swap pairs and the Y axis exhibits the average log ratio of four forward labeled arrays. We used this information for detecting differentially expressed genes, of which the additionally detected genes were validated by real-time RT-PCR.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.317-320
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• 2000

In this paper, a 0.5W, 2GHz high-efficiency class A power amplifier using the dynamic bias control is proposed. First of all, the drain bias control amplifier is analyzed theoretically and designed with commercial devices. Simulation results show that the proposed amplifier has a significant improved efficiency, compared to fixed bias power amplifier.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.195-199
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• 2002

This paper describes the effect of substrate back bias of CMOS Inverter. When the substrate back bias applied in body, the MOS transistor threshold voltage increased and drain saturation current decreased. The back gate reverse bias or substrate bias has been widely utilized and the following advantage has suppressing subthreshold leakage, lowering parasitic junction capacitance, preventing latch up or parasitic bipolar transistor, etc. When the reverse voltage applied substrate, this paper stimulated the propagation delay time CMOS inverter.