• Journal of the Korea Society of Computer and Information
• /
• v.14 no.2
• /
• pp.169-180
• /
• 2009

The conventional paper retrieval is the keyword-based search and as a huge amount of data be published, this search becomes more difficult in retrieving information that user want to find. In order to search for information to the user's intent, we need to introduce semantic Web that represents semantics of Web document resources on the Internet environment as ontology and enables the computer to understand this ontology. Therefore, we describe a paper retrieval system through OWL(Ontology Web Language) ontology-based reason in this paper. We build the paper ontology based on OWL which is new popular ontology language for semantic Web and represent the correlation among diverse paper properties as the DL(description logic) query, and then this system infers the correct results from the paper ontology by using the DL query and makes it possible to retrieve information intelligently. Finally, we compared our experimental result with the conventional retrieval.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.4
• /
• pp.781-788
• /
• 2017

This paper proposes a new algorithm for comparing amplitude between multiple digital input signals and its digital logic architecture. After simultaneously comparing multiple inputs, the proposed algorithm can provide the information of the largest (or smallest) value among them by using a simple digital logic function. The drawback of the method is to increase hardware resource. To overcome this we propose a reuse method of the overlapped logic operation. The proposed method focuses on enhancing the operational clock frequency, in other words decreasing combinational delay time. After implementing the comparing method with HDL (hardware description language), we experiment on it with environment of Cyclone III EP3C40F324A7 FPGA of Altera Inc. In case of 4 input signals, it can increase the operational speed as mush as 1.66 times with 1.20 times the hardware resource. In case of 8, it can also have 2.29 times the clock frequency and 2.15 times the hardware resource.

• Korean Institute of Interior Design Journal
• /
• v.17 no.6
• /
• pp.120-127
• /
• 2008

Korean space design image is a kind of writing as well as one of the sign that dissembles itself as a direct transcript of what it represents. Moreover it is pictorial representation and notions such as mental and perceptual imaginary. Significance of Iconology lies in how we transform image and the imagination that produces it into power of trust and respect. From this point of view, the process of this study is illustrated as follows: At first, this study search out concept of archetype, collective unconsciousness and collective representation that found principles on basic theory for interpretation of korean space icon. Secondly, it mentions theoretical background of iconological contents and structure. And it clarifies Iconology as a method that is applicable logic for Korean space design. Finally, as an analysis of korean space design, this study analyse in three steps that are pre-iconological description, iconological analysis, iconological interpretation each in terms of modernization at regional korean space design. In the step of the pre-iconological description, it describe visual representative style based on era and place. In the step of the iconological analysis, the typical structure is classified in status, vernacular, ethnic, traditional. In the step of the iconological interpretation, connotation is categorized into allegory, multivalence, potential. Through this process, this study suggest that iconology is an appropriate analysis system of Korean space design images that represent symbols combined with our collective emotion.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.4
• /
• pp.127-137
• /
• 1989

This paper describes hardware flow-chart and SDL-II, which are register-transfer level, to automate logic design. Hardware flow-chart specifies behavioral and structural charaterstics of generalized FSMs (Finite State Machine) usin the modified ASM (Algorithmic State Machnine) design techniques. SDL-II describes the hardware flow-chat which specifies the control and the data path of ASIC(Application Specific IC). Also many examples are enumerated to illustrate the features of hardware flow-chart and SDL-II.

• Korean journal of communication and information
• /
• v.71
• /
• pp.250-273
• /
• 2015

The phenomenology of communication represents a starting point in the union of consciousness and experience, analogue and digit, expression and perception, person and lived-world, rhetoric and ethic, constitute human communication. A phenomenological definition of communication requires that analysis proceed through a phenomenological description, reduction, interpretation. This analysis thus far has taken up the general issue of fact versus value, consisting in a subdivision into intention and punctuation on the factual side, and convention and legitimation on the value side. It has treated of the relationships among intention and metaphysics, punctuation and epistemology, convention and logic, and legitimation and axiology.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.8
• /
• pp.2179-2189
• /
• 1998

This paper presents the methodolog~- to improve the computatIon efficiency of the simulation by developing the concept of the dynamic preservatIon and reurilization of the state transitions. The computation COst is emormous for the simulation of hardware described in hardware description languages including VHDL Analyzing the process of simulation precisely, we have found that the number of the pattems for the state transition is limited if the sizes of hardware modules are determined properly. The pattems are preserved dynamically when they appeared first, and are utilized in later simulation in order to reduce the simulation costs. In this study, the efficiency of the present method was verified using case studies for the simulation.

• Journal of the Korean Society of Systems Engineering
• /
• v.14 no.2
• /
• pp.41-48
• /
• 2018

This paper describes the systems engineering development process for the Departure from Nucleate Boiling Ratio (DNBR) algorithm using FPGA. Current Core Protection Calculator System (CPCS) requirement and DNBR logic are analyzed in the reverse engineering phase and the new FPGA based DNBR algorithm is designed in the re-engineering phase. FPGA based DNBR algorithm is developed by VHSIC Hardware Description Language (VHDL) in the implementation phase and VHDL DNBR software is verified in the software Verification & Validation phase. Test cases are developed to perform the software module test for VHDL software modules. The APR 1400 simulator is used to collect the inputs data in 100%, 75%, and 50% reactor power condition. Test input signals are injected to the software modules following test case tables and output signals are compared with the expected test value. Minimum DNBR value from developed DNBR algorithm is validated by KEPCO E&C CPCS development facility. This paper summarizes the process to develop the FPGA-based DNBR calculation algorithm using systems engineering approach.

• Journal of Sensor Science and Technology
• /
• v.12 no.1
• /
• pp.44-50
• /
• 2003

A security system consisted of an infrared sensor and PLD(Programmable Logic Device) was fabricated to prevent an intruder. The fabricated system detect the intruder using infrared sensor and has password key pad to permit someone to enter the house and office. The control circuit of the system is designed by VHDL(Very high speed integrated Hardware Description Language). The system was demonstrated in various conditions and the output signals were displayed in LCD, LED, buzzer and so on. This designed system in this paper has a advantage to supplement additional function with ease.

• Proceedings of the KIEE Conference
• /
• 2001.11c
• /
• pp.284-287
• /
• 2001

In this paper, we designed and implemented a precise pulse motor control chip that generates the parabolic speed pattern. This chip can control step motor[1], DC servo[2] and AC servo motors at high speed and precisely. It can reduce the mechanical vibration to the minimum at the change point of a degree of acceleration. Because the parabolic speed pattern has the continuous acceleration change. In this paper, we present the pulse generation algorithm and the parabolic pattern speed generation. We verify these algorithm using visual C++. We designed this chip with VHDL(Very High Speed Integrated Circuit Hardware Description Language) and executed a logic simulation and synthesis using Synopsys synthesis tool. We executed the pre-layout simulation and post-layout simulation with Verilog-XL simulation tool. This chip was produced with 100 pins, PQFP package by 0.35 um CMOS process and implemented by completely digital logic. We developed the hardware test board and test program using visual C++. We verify the performance of this chip by driving the servo motor and the function by GUI(Graphic User Interface) environment.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.9 no.2
• /
• pp.55-61
• /
• 2013

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). Contemporary FPGAs have large resources of logic gates and RAM blocks to implement complex digital computations. In this paper, we implement a system of digital instrumentation using FPGA. This system consists of the trigger part, memory address controller part, control FSM part, Encoder part, LCD controller part. The hardware implement using FPGA and the verification of the operation is done in a PC simulation. The proposed hardware was mapped into Cyclone III EP2C5Q208 from Altera and used 1,700(40%) of Logic Element (LE). The implemented circuit used 24,576-bit memory element with 6-bit input signal. The result from implementing in hardware (FPGA) could operate stably in 140MHz.