• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.821-825
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• 2004

The a-Si：H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si：H TFTs is inverted staggered. The gate electrode is formed by patterning with length of 8 ${\mu}m∼16 ${\mu}m. and width of 80∼200 ${\mu}m after depositing with gate electrode (Cr) 1500 under coming 7059 glass substrate. We have fabricated a-SiN：H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN：H (2000 ), a-Si：H(2000 ) and n+a-Si：H (500). We have deposited n+a-Si：H ,NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si：H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si：H TFTs decreasing parasitic capacitance of source-drain has channel length of 8 ~20 ${\mu}m and channel width of 80∼200 ${\mu}m. And it shows drain current of 8 ${\mu}A at 20 gate voltages, Ion/Ioff ratio of 108 and Vth of 4 volts.

• Progress in Superconductivity
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• v.14 no.1
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• pp.30-33
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• 2012

We have grown $MgB_2$ superconducting thin films on the SiC buffer layers by means of hybrid physical-chemical vapor deposition (HPCVD) technique. Prior to that, SiC was first deposited on $Al_2O_3$ substrates at various temperatures from room temperature to $600^{\circ}C$ by using the pulsed laser deposition (PLD) method in a vacuum atmosphere of ${\sim}10^{-6}$ Torr pressure. All samples showed a high transition temperature of ~40 K. The grain boundaries of $MgB_2$ samples with SiC layer are greater in amount, compare to that of the pure $MgB_2$ samples. $MgB_2$ with SiC buffer layer samples show interesting change in the critical current density ($J_c$) values. Generally, at both 5 K and 20 K measurements, at lower magnetic field, all $MgB_2$ films deposited on SiC buffer layers have low $J_c$ values, but when they reach higher magnetic fields of nearly 3.5 Tesla, $J_c$ values are enhanced. $MgB_2$ film with SiC grown at $600^{\circ}C$ has the highest $J_c$ enhancement at higher magnetic fields, while all SiC buffer layer samples exhibit higher $J_c$ values than that of the pure $MgB_2$ films. A change in the grain boundary morphologies of $MgB_2$ films due to SiC buffer layer seems to be responsible for $J_c$ enhancements at high magnetic fields.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.257-257
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• 2010

One of the critical issues for applications of flexible organic thin film transistors (OTFTs) for flexible electronic systems is the electrical stabilities of the OTFT devices, including variation of the current on/off ratio ($I_{on}/I_{off}$), leakage current, threshold voltage, and hysteresis, under repetitive mechanical deformation. In particular, repetitive mechanical deformation accelerates the degradation of device performance at the ambient environment. In this work, electrical stabilities of the pentacene organic thin film transistors (OTFTs) employing multi-stack hybrid encapsulation layers were investigated under mechanical cyclic bending. Flexible bottom-gated pentacene-based OTFTs fabricated on flexible polyimide substrate with poly-4-vinyl phenol (PVP) dielectric as a gate dielectric were encapsulated by the plasma-deposited organic layer and atomic layer deposited inorganic layer. For cyclic bending experiment of flexible OTFTs, the devices were cyclically bent up to $10^5$ times with 5mm bending radius. In the most of the devices after $10^5$ times of bending cycles, the off-current of the OTFT with no encapsulation layers was quickly increased due to increases in the conductivity of the pentacene caused by doping effects from $O_2$ and $H_2O$ in the atmosphere, which leads to decrease in the $I_{on}/I_{off}$ and increase in the hysteresis. With encapsulation layers, however, the electrical stabilities of the OTFTs were improved significantly. In particular, the OTFTs with multi-stack hybrid encapsulation layer showed the best electrical stabilities up to the bending cycles of $10^5$ times compared to the devices with single organic encapsulation layer. Changes in electrical properties of cyclically bent OTFTs with encapsulation layers will be discussed in detail.

• Korean Journal of Materials Research
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• v.15 no.11
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• pp.705-710
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• 2005

NIL (nanoimprint lithography) technique has demonstrated a high potential for wafer size definition of nanometer as well as micrometer size patterns. During the replication process by NIL, the stiction between the stamp and the polymer is one of major problems. This stiction problem is moi·e important in small sized patterns. An antistiction layer prevents this stiction ana insures a clean demolding process. In this paper, we were using a TCP (transfer coupled plasma) equipment and $C_4F_8$ as a precursor to make a Teflon-like antistiction layer. This antistiction layer was deposited on a 6 inch silicon wafer to have nanometer scale thicknesses. The thickness of deposited antistiction layer was measured by ellipsometry. To optimize the process factor such as table height (TH), substrate temperature (ST), working pressure (WP) and plasma power (PP), we were using a design of experimental (DOE) method. The table of full factorial arrays was set by the 4 factors and 2 levels. Using this table, experiments were organized to achieve 2 responses such as deposition rate and non-uniformity. It was investigated that the main effects and interaction effects between parameters. Deposition rate was in proportion to table height, working pressure and plasma power. Non-uniformity was in proportion to substrate temperature and working pressure. Using a response optimization, we were able to get the optimized deposition condition at desired deposition rate and an experimental deposition rate showed similar results.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.96.2-96.2
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• 2010

The surface morphology and structural properties of polycrystalline silicon (poly-Si) films made in-situ aluminum induced crystallization at various substrate temperature (300~600) was investigated. Silicon films were deposited by hot-wire chemical vapor deposition (HWCVD), as the catalytic or pyrolytic decomposition of precursor gases SiH4 occurs only on the surface of the heated wire. Aluminum films were deposited by DC magnetron sputtering at room temperature. continuous poly-Si films were achieved at low temperature. from cross-section TEM analyses, It was confirmed that poly-Si above $450^{\circ}C$ was successfully grown on and poly-Si films had (111) preferred orientation. As substrate temperature increases, Si(111)/Si(220) ratio was decreased. The electrical properties of poly-Si film were investigated by Hall effect measurement. Poly-Si film was p-type by Al and resistivity and hall effect mobility was affected by substrate temperature.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.91-94
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• 2002

Textured Ce$O_{2}$ buffers for YBCO coated conductors were deposited on biaxially textured Ni substrate by metalorganic chemical vapor deposition The texture of deposited Ce$O_{2}$ films was varied with deposition temperature(T) and oxygen partial pressure($Po_{2}$). ($\ell$ 00) textured Ce$O_{2}$ films were deposited at T= 500~$520^{\circ}C$, $Po_{2}$= 0.90~3.33 Torr. The growth rate of the Ce$O_{2}$ films was 150~200 nm/min at T= $520^{\circ}C$ and $Po_{2}$= 2.30 Torr, which was much faster than that prepated by other physical deposition method.

• Journal of the Korean Vacuum Society
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• v.2 no.4
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• pp.474-479
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• 1993

Submicron contact hole filling with aluminum alloys has been achieved with a multistep metallization method, which utilizes a metal " flow" or self-diffusion process at elevated temperatures after the metal was sputter-deposited. A multi-chamber, modular sputtering system was employed to deposit aluminum alloys and subsequently to anneal the deposited metal films under vacuum at high temperatures. The film were deposited on 200 mm wafers with planar, dc magnetron sputtering sources without anysubstrate bias. The basic process steps studied for the multistep metallization include an initial layer deposition at low temperatures less than $100^{\circ}C$, and an annealin gstep at elevated temperatures, between 450 and $550^{\circ}C$. The degree of planarization or step coverage was dependent strongly upon the temperature and time of the flow step and complete filling of the submicron contacts with aluminum alloys was achieved. Responsible mechanisms for the enhancement in step coverge and factros determining uniform and reproducible flow of aluminum alloys during the high temperauture step are discussed.discussed.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.3
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• pp.109-115
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• 2003

Diamond-like carbon (DLC) films are deposited at room temperature using a filtered cathodic vacuum arc (FCVA) technique. The influence of negative bias voltage (applied to the substrate from 0 to -250V) on the $sp^3$ hybridized carbon fraction is examined by Raman spectroscopy and x-ray photoelectron spectroscopy (XPS) for C 1s core peak. For the first time, depth profile of C 1s, Si 2p, and O 1s XPS peaks for the deposited DLC film are obtained. DLC film is modeled as a multilayered structure. composing of surface, bulk, and interface. In addition, the x-ray reflectivity (XRR) is proposed as a method for estimating the density, surface roughness, and thickness of each layer constituting the DLC film. The estimated thickness of DLC film is in good agreement with the result obtained from the transmission electron microscope (TEM) measurement.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.254-257
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• 2008

We have investigated the effect of source/drain electrode deposition method on a performance of top gate structured ZnO TFT performance. TFT using S/D of ITO film, consisted of bi-layer which deposited by ion beam assisted sputtering at the initial stage then deposited by DC magnetron sputtering, showed better performance compared to that using S/D of ITO deposited by just DC magnetron sputtering. Two ITO films exhibited different grain shapes and these resulted in different etching properties. We also suspect that charge trapping on the glass substrate (back channel) during the ITO film deposition may influence the characteristics of top gate structured ZnO TFT.

• Journal of the Korean Ceramic Society
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• v.31 no.10
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• pp.1115-1122
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• 1994

ZT/PZT/ZT multi-layered thin films were deposited on silicon substrate by co-sputtering method for FEMFET device application. Effects of Pb/(Zr+Ti) ratio, films thickness, annealing conditions and substrate temperature on the ferroelectric behavior of the multi-layered films were studied. The best memory device characteristics with leakage current of 2$\times$10-8 A/$\textrm{cm}^2$ and breakdown field of about 1 MV/cm could be obtained with ZT(250 $\AA$) / PZT(1000 $\AA$)/ZT(750 $\AA$) multi-layered thin film deposited at 35$0^{\circ}C$ and post-annealed at $700^{\circ}C$ for 120 sec by RTA(Rapid Thermal Annealing).