• Journal of the Korean Geographical Society
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• v.44 no.4
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• pp.463-480
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• 2009

The weathering properties and provenance of loess-paleosol sequence deposited on gravel layer of river terrace in Bongdong-eup, Wangju-gun, Jeonbuk Province are examined using soil analysis, magnetic susceptibility measurement, grain size and element analysis. The Bongdong section consists of, from top to bottom, Layer 1(paleosol), Layer 2(loess), Layer 3(paleosol) and the gravel layer of river terrace. The magnetic susceptibility values show the systematic variations in the sequence and the results of grain size analysis reveal that the sequence was deposited by not fluvial or slope process, but eolian process, and that contains finer materials than the Daecheon loess and Chinese Loess Plateau. Among the results of soil analysis, organic contents indicate systematic variations similar to the magnetic susceptibility. The wet soil colors further reflect the characteristics of the sequence rather than the dry soil colors. Based on the analytical results of major and rare earth elements, the eolian materials contained in the sequence were deposited by the materials originated from the areas where the Chinese Loess Plateau has been originated or the reworked materials from the Chinese Loess Plateau, and after the depositions, the materials experienced the intensive chemical weathering under the humid-warm climatic conditions in the Korean Peninsula.

• Journal of Information Display
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• v.10 no.4
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• pp.137-142
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• 2009

Transparent top-gate Al-Zn-Sn-O (AZTO) thin-film transistors (TFTs) with an $Al_2O_3$ protective layer (PL) on an active layer were studied, and a transparent 2.5-inch QCIF+AMOLED (active-matrix organic light-emitting diode) display panel was fabricated using an AZTO TFT backplane. The AZTO active layers were deposited via RF magnetron sputtering at room temperature, and the PL was deposited via two different atomic-layer deposition (ALD) processes. The mobility and subthreshold slope were superior in the TFTs annealed in vacuum and with oxygen plasma PLs compared to the TFTs annealed in $O_2$ and with water vapor PLs, but the bias stability of the TFTs annealed in $O_2$ and with water vapor PLs was excellent.

• Korean Journal of Materials Research
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• v.16 no.1
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• pp.30-36
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• 2006

A novel method was proposed to grow an epitaxial $CoSi_2$ on (100)Si substrate. A $CoN_x$ interlayer was deposited by reactive sputtering of Co in an Ar+$N_2$ flow. From the Ti/Co/$CoN_x$/Si structure, a uniform and thin $CoSi_2$ layer was epitaxially grown on (100)Si by annealing above $700^{\circ}C$. Two amorphous layers were found at the $CoN_x$/Si interface, where the top layer has a silicon nitride (Si-N) bonding state with some Co content and the bottom layer has a Co-Si intermixing state. The SiNx amorphous layer seems to play a critical role of suppressing the diffusion of Co into Si substrate for the direct formation of epitaxial $CoSi_2$.

• Bulletin of the Korean Chemical Society
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• v.29 no.4
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• pp.842-846
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• 2008

Layer-by-layer assembled multilayers of poly(ethersulfone)s were deposited on the surface of Nafion membrane for the application of direct methanol fuel cells (DMFC). Aminated poly(ethersulfone) (APES) and sulfonated poly(ethersulfone) (SPES) were used as a polycation and a polyanion for fabrication of the multilayer films. UV/Vis absorption spectroscopy verified a linear build-up of the multilayers of APES and SPES on the surface of Nafion. Thin multilayer films deposited on the Nafion membrane enabled methanol permeability of the membrane to decrease by 78% in comparison with the pristine Nafion. The performance of DMFCs in concentrated methanol was highly enhanced by using the multilayer modified Nafion.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.9-10
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• 2007

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition(ALD). And we studied the electrical characterization of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3\;at\;350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Through TEM(Transmission Electron Microscope), XRD(X-ray Diffraction), capacitance-voltage(C-V) and current-voltage(I-V) analysis, the role of thin Hf metal layer for the better $HfO_2$/Si interface property was investigated.

• Journal of the Korean institute of surface engineering
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• v.32 no.1
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• pp.61-66
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• 1999

The Spin-dependent tunneling magnetoresistance (TMR) effect was observed in $NiFe/Al_2O_3$/Co thin films. The samples were prepared by magnetron sputtering in a system with a base pressure of $3\times10^{-6}$Torr. the insulating $Al_2O_3$layer was prepared by r.f. plasma oxydation method of a metallic Al layer. The ferromagnetic and insulating layers were deposited through metallic masks to produce the cross pattern form. The junction has an active area of $0.3\times0.3\textrm{mm}^2$ and the $Al_2O_3$layer is deposited through a circular mask with a diameter of 1mm. It is very important that insulating layer is formed very thinly and uniformly in tunneling junction. The ferromagnetic layer was fabricated in optimum conditions and the surface of that was very flat, which was observed by AFM. Tunneling junction was confirmed through nonlinear I-V curve. $NiFe/Al_2O_3$/Co junction was observed for magnetization behavior and magnetoresistance property and magnetoresistance property is dependent on magnetization behavior and magnetoresistance property and magnetoresistance property is dependent on magnetization behavior of t재 ferromagnetic layer. The maximum magnetoresistance ratio was about 6.5%.

• Progress in Superconductivity
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• v.8 no.1
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• pp.27-32
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• 2006

[$YBa_2Cu_3O_{7-x}$] thin films were deposited on various buffered-templates by a metal organic chemical vapor deposition(MOCVD). Three different templates of $CeO_2/YSZ/CeO_2/pure-Ni(CYC),\;CeO_2/YSZ/Y_2O_3/Ni-3at.%W(YYC)$ and $CeO_2/IBAD-YSZ$/stainless steel were used. The Ni and Ni-W alloy tapes were biaxially textured by cold rolling and annealing heat treatment. The dense YBCO films were grown on both the IBAD and YYC templates with no microcrack, while the YBCO films on the CYC templates were grown with the formation of microcracks and NiO. The YBCO film on the YYC template showed the higher $I_c$ than that on CYC template. Especially, the IBAD templates with a thin $CeO_2$(type I) and thick $CeO_2$(type II) top layer were used to compare the deposition nature of the YBCO on them. Comparing the current property of the YBCO films on IBAD templates, the YBCO film deposited on thick $CeO_2$ layer was better than the film on thin $CeO_2$ layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.188-188
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Meta Oxide Semiconductor) based electronic devices, the electronic devices, become much faster and smaller size that are promising property of semiconductor market. However, very narrow interconnect line width has some disadvantages. Deposition of conformal and thin barrier is not easy. And metallization process needs deposition of diffusion barrier and glue layer for EP/ELP deposition. Thus, there is not enough space for copper filling process. In order to get over these negative effects, simple process of copper metallization is important. In this study, Cu-V alloy layer was deposited using of DC/RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane SiO2/Si bi-layer substrate with smooth surface. Cu-V film's thickness was about 50 nm. Cu-V alloy film deposited at $150^{\circ}C$. XRD, AFM, Hall measurement system, and AES were used to analyze this work. For the barrier formation, annealing temperature was 300, 400, $500^{\circ}C$ (1 hour). Barrier thermal stability was tested by I-V(leakage current) and XRD analysis after 300, 500, $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However vanadium-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Therefore thermal stability of vanadium-based diffusion barrier is desirable for copper interconnection.

• Korean Journal of Materials Research
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• v.12 no.3
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• pp.225-230
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• 2002

Sn was selected as an alloying element of Cu. The Cu-Sn thin layers were deposited on the Si substrates by the electroplating method and their properties were studied. By rapidly thermal annealing(RTA) up to 40$0^{\circ}C$ after electroplating, sheet resistance decreased and adhesion strength increased, but that trend was reversed at the 50$0^{\circ}C$ RTA. Cu-Sn particles grew dense and the surface was uniform up to 40$0^{\circ}C$, but at 50$0^{\circ}C$, empty area was introduced and the surface became rough owing to oxidation and particle coarsening and agglomeration. Deposited layer contained significant amount of Si, while pure Cu-Sn layer with the composition ratio of 90:10 was present only on the top surface. However, no significant change in the Cu composition within alloy layers occured by the RTA regardless of its temperature. This indicates that the Cu diffusion into the Si was suppressed by the presence of Sn.

• Transactions on Electrical and Electronic Materials
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• v.3 no.1
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• pp.4-8
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• 2002

The typical mold method for FED (field emission display) fabrication is used to form a gate electrode, a gate oxide layer, and emitter tip after fabrication of a mold shape using wet-etching of Si substrate. However, in this study, new mold method using a side wall space structure was developed to make sharp emitter tips with the gate electrode. In new method, gate oxide layer and gate electrode layer were deposited on a Si wafer by LPCVD (low pressure chemical vapor deposition), and then BPSG (Boro phosphor silicate glass) thin film was deposited. After then, the BPSG thin film was flowed into the mold at high temperature in order to form a sharp mold structure. TiN was deposited as an emitter tip on it. The unfinished device was bonded to a glass substrate by anodic bonding techniques. The Si wafer was etched from backside by KOH-deionized water solution. Finally, the sharp field emitter array with gate electrode on the glass substrate was formed.