• Title/Summary/Keyword: demodulator

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Low-Noise Detector Design for Measuring the Electric Conductivity of Liquids (액체의 전기 전도도 측정을 위한 저잡음 검출기 설계)

  • Kim, Nam Tae
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.9
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    • pp.287-292
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    • 2012
  • In this paper, design of a conductivity detector using a synchronous demodulation is presented to detect the electric conductivity of liquids with low noise. For the purpose, the detector is constructed by the combination of a carrier generator, conductivity detecting cell, and synchronous demodulator. The signal-to-noise ratio(SNR) of the detector is improved by adjusting the frequency bandwidth of the demodulator, whereby infinitesimal conductivity signals can easily be measured under various noise environments. As an application example, a conductivity detector, which is applied to the air monitoring in a fabrication process of semiconductor chips, is designed using the synchronous demodulation. The validity of the design technique is verified by experiments. Since experimental results are shown to approach the design performance of the detector, the synchronous demodulation proves to be useful to the design of a conductivity detector for measuring the infinitesimal electric conductivity of liquids.

A Design of High Speed Infrared Optical Data Link IC (고속 적외선 광 송수신 IC 설계)

  • 임신일;조희랑;채용웅;유종선
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.12B
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    • pp.1695-1702
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    • 2001
  • This paper describes a design of CMOS infrared (IR) wireless data link IC which can be used in IrDA(Infrared Data Association) application from 4 Mb/s to 100 Mb/s The implemented chip consists of variable gain transimpedance amplifier which has a gain range from 60 dB to 100 dB, AGC (automatic gain control) circuits, AOC(automatic offset control) loop, 4 PPM (pulse position modulation) modulator/demodulator and DLL(delay locked loops). This infrared optical link If was implemented using commercial 0.25 um 1-poly 5-metal CMOS process. The chip consumes 25 mW at 100 Mb/s with 2.5 V supply voltage excluding buffer amplifier. The die area of prototype IC is 1.5 mm $\times$ 1 mm.

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The Performance of a Non-Decision Directed Clock Recovery Circuit for 256 QAM Demodulator (256-QAM 복조를 위한 NDD 클럭복원회로의 성능해석)

  • 장일순;조웅기;정차근;조경록
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.1A
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    • pp.27-33
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    • 2000
  • Gardner’s algorithm is one of the useful algorithm for NDD(Non-Decision Directed) symbol synchronization in PAM communications. But the algorithm has a weak point such as pattern noises increasing in multi-level PAM. To insert a pre-filter in the algorithm is able to reduce timing jitter and pattern noise. In this paper, we analyze statistical properties of NDD algorithm to find an optimal parameter of the pre-filter for improving timing jitter and PLL locking. As a simulation result, optimum value of pre-filter parameter, $\beta$, is 0.3 and 0.5 at the roll off factor of the channel, $\alpha$, is 0.5 and 1.0, respectively. Optimum parameters of the pre-filter for clock synchronization of all-digital 256-QAM demodulator is shown in the results.

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VLSI Implementation of CORDIC-Based Digital Quadrature Demodulator (CORDIC을 이용한 디지탈 Quadrature 복조기의 VLSI 구현)

  • 남승현;성원용
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.7
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    • pp.1718-1731
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    • 1998
  • Digital quadrature demodulator is needed for the coherent demodulation in the digital communication systems such as Binary Phase-Shift-Keying, Quadrature Phase-Shift-Keying, and Quadrature Anmplitude Modulation. Conventaionally, the DDFS (Direct Digital Frequency Synthsizer) is used for generating the carrier signal and seperate multi-pliers are used for mixing. And the DDFS is implemented using the ROM (Read Only Memory), which can be a bottle-neck neck when the fast-speed and small-area implementation is required. A new architecture is developed, which employs the circular rotation mode of the CORDIC algorithm for signal mixing as well as carrier generation. To optimize the hardware design parameters, the finiteword-length effects of the proposed implementation arachitecture are analyzed in comparison with a conventional ROM-based architecture. The hardware costs are also estimated, which showed that the proposed architecture occupies only a third of the area of the conventional ROM-based architecture for the same performance. A full-custom VLSI is developed using the proposed architecture.

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A Design of the Demapper Using Channel State Information for COFDM Demodulator (COFDM 복조기에서의 채널상태정보를 이용한 디매퍼의 설계)

  • Kang, Kyung-Jin;Lee, Weon-Cheol
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.36S no.10
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    • pp.21-29
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    • 1999
  • This paper is concerning about the demapping method using the pilots inserted in transmitter in COFDM(Coded Orthogonal Frequency Division Multiplexing) demodulator which is the standard transmission method of terrestrial digital TV system in Europe(DVB-T). We have presented a simple and efficient method of CSI(Channel State Information) generation and demapping method using CSI. The CSI was derived from the pilot carriers inserted with comb-type among the received active carriers, which is defined as a SNR. From the simulation results for the 3 different constellations of the receiver, we could confirm that the system performance comparing with conventional soft decision method has been improved under DVB-T standard Rayleigh and Ricean fading channel.

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Design of Digital Transmitter and Receiver Modules in ILS (항공 계기착륙 디지털 송수신 모듈 설계)

  • Choi, Jong-Ho
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.4 no.4
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    • pp.264-271
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    • 2011
  • ILS(Instrument Landing System) is the international standard system for approach and landing guidance. ILS was adopted by ICAO(International Civil Aviation Organization) in 1947 and is currently being used in commercial systems. To design the digital transmitter and receiver modules that can be mounted in the integrated ILS, we propose the digital design methods of digital double AM modulator and demodulator using FPGA chip, DDS(Direct Digital Synthesizer) for generation of sampling clock, demodulator of DDC(Digital Down Converter) structure, and spectrum analyzer using DSP chip. We demonstrate the efficiency of the proposed design method through experiments using developed transmitter and receiver modules. This system can be used as a high-performance commercial system.

A Study for SNR Degradation of OFDM Demodulator Output by Impulsive Noise in Power Line Communication Channel (전력선 채널 Impulsive Noise에 의한 OFDM Demodulator 출력 SNR 열화에 관한 연구)

  • Oh, Hui-Myoung;Choi, Sung-Soo;Kim, Young-Sun;Kim, Kwan-Ho;Whang, Keum-Chan
    • Proceedings of the KIEE Conference
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    • 2007.07a
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    • pp.1880-1881
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    • 2007
  • 전력선 통신 채널에는 특징적으로 충격 잡음이 존재하며, 전력선 통신 시스템의 성능 열화에도 많은 영향을 준다. 이는 일반적인 배경 잡음에 비해 많게는 수십 dB 이상의 레벨을 가지면서, 임의 시간적으로 발생함으로써 추정 및 제어 또한 어렵기 때문이며, 전력선 통신 시스템이 Mbps급으로 고속화 되면서 주파수 대역이 확장되고, 확장된 대역상에 다중 반송파를 이용하여 대용량의 데이터를 전송하는 변복조기법들이 적용됨에 따라, 시간 영역에서 비교적 짧은 시간 동안 존재하는 충격 잡음이 주파수 영역에서 사용 주파수 전체 대역상에 영향을 줌으로써 시스템 전체 성능 저하의 큰 요인이 되고 있다. 본 논문에서는 이러한 충격 잡음이 고속 전력선 통신 시스템에서 사용되는 OFDM(또는 DMT) 방식 수신기의 복조기 출력단 SNR에 미치는 영향을 분석 및 단순화하고, 시뮬레이션을 통해 검증한다.

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A 13.56 MHz Radio Frequency Identification Transponder Analog Front End Using a Dynamically Enabled Digital Phase Locked Loop

  • Choi, Moon-Ho;Yang, Byung-Do;Kim, Nam-Soo;Kim, Yeong-Seuk;Lee, Soo-Joo;Na, Kee-Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.1
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    • pp.20-23
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    • 2010
  • The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

Radiotelemetry for ECG and Event Signals Using FDM (주파수분할 다중방식에 의한 심전신호 및 부가정보신호 무선전송)

  • 이훈규;박동철
    • Journal of Biomedical Engineering Research
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    • v.21 no.4
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    • pp.345-351
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    • 2000
  • This study is to dvelop a radiotelemetry system to transmit and receive ECG (electrocardiograph) and event signals by using the frequency division multiplexing(FDM) technique. ECG signal sensed by the electrodes is amplified and added to the event signals acting in different frequency range for lead-off, nurse call and low level battery by using FDM. The sub-carrier oscillator using Colpitts circuits and main carrier frequency which is multiplied is frequency modulated by this superhetrodyne technique, and demodulated from the compose IF signal through the quadrature demodulator. A pulse counter demodulator and filtering circuits extract the original ECG and event signals.

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Implementation of Real-time Stereo Frequency Demodulator Using RTL-SDR (RTL-SDR을 이용한 스테레오 주파수 변조 방송의 실시간 수신기 구현)

  • Kim, Young-Ju
    • Journal of Broadcast Engineering
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    • v.24 no.3
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    • pp.485-494
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    • 2019
  • A software-driven real-time frequency de-modulator is implemented with the aid of universal-serial-bus (USB) type software defined radio dongle. An analog stereo frequency modulation (FM) broadcast signal is down-converted to the basedband analog signal then converted to digital bit streams in the USB dongle. Computer software such as Matlab, Python, and GNU Radio manipulates the incoming bit streams with the technique of digital signal processing. Low pass filtering, band pass filtering, decimation, frequency discriminator, double sideband amplitude demodulation, phase locked loop, and deemphasis function blocks are implemented using such computer languages. Especially, GNU Radion is employed to realize the real-time demodulator.