• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.303-309
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• 2016

This paper presents a channel-adaptive rate control algorithm for low delay video coding. The main goal of the proposed method is to adaptively use the unknown available channel bandwidth while reducing the end-to-end delay between encoder and decoder. The key idea of the proposed algorithm is for the status of the encoder buffer to indirectly reflect the mismatch between the available channel bandwidth and the generated bitrate. Hence, the proposed method fully utilizes the unknown available channel bandwidth by monitoring the encoder buffer status. Simulation results show that although the target bitrate mismatches the available channel bandwidth, the encoder efficiently adapts the given available bandwidth to improve the peak signal-to-noise ratio.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.06a
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• pp.1176-1185
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• 2005

A linear power amplifier is particularly emphasized on the system using a linear modulations, such as 16QAM and QPSK with pulse shaping, because intermodulation distortion which causes adjacent channel interference and co-channel interference is mostly generated in a nonlinear power amplifier. In this paper, parameters of a linearization loop, such as an amplitude imbalance, a phase imbalance and a delay mismatch, are briefly analyzed to get a specific cancellation performance and linearization bandwidth. Experimental results are presented for IMT-2000 frequency band. The center frequency of the feedforward amplifier is 2140 MHz with 60 MHz bandwidth. When the average output power of feedforward amplifier is 20 Watt, the intermodulation cancellation performance is more than 21 dB. In this case, the output power of feedforward amplifier reduced 3.5 dB because of extra delay line loss and coupling loss. The feedforward amplifier efficiency is more than 7.2 % for multicarrier signals, 59 dBc for ACPR.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2164-2166
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• 2002

This paper present a controller design scheme for time-delay system. The Smith Predictor has been proposed to solve the problem of time-delay. But this structure has a condition that parameters of plant and model have to be matched accurately. Because of this condition, it is not applied broadly in practical industrial process field. In this paper, the 2nd-order model with dead-time is used as plant model of the Smith Predictor and a main controller is designed by using the effect of mismatch between plant and model.

• Journal of Navigation and Port Research
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• v.28 no.2
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• pp.149-154
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• 2004

A linear power amplifier is particularly emphasized on the system using a linear modulations, such as 16QAM and QPSK with pulse shaping, because intermodulation distortion which causes adjacent channel interference and co-channel interference is mostly generated in a nonlinear power amplifier. In this paper, parameters of a linearization loop, such as an amplitude imbalance, a phase imbalance and a delay mismatch, are briefly analyzed to get a specific cancellation performance and linearization bandwidth Experimental results are presented for IMT-2000 frequency band The center frequency of the feedforward amplifier is 2140MHz with 60MHz bandwidth When the average output power of feedforward amplifier is 20 Watt, the intermodulation cancellation performance is more than 28dB. In this case, the output power of feedforward amplifier reduced 3.5dB because of extra delay line loss and coupling loss. The feedforward amplifier efficiency is more than 7% for multicarrier signals.

• Journal of Electrical Engineering and Technology
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• v.2 no.2
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• pp.165-171
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• 2007

This paper proposes a new islanding detection method for inverter-interfaced distributed generators (DG). To detect islanding conditions, this paper calculates the phase angle variation of the system voltage by using the phase-locked loop (PLL) in the inverter controllers. Because almost all inverter systems are equipped with the PLL, the implementation of this method is fairly simple and economical for inverter-interfaced DGs. The detection time can also be shortened by reducing communication delay between the relays and the DGs. The proposed method is based on the fact that islanding conditions result in the frequency and voltage variation of the islanded area. The variation depends on the amount of power mismatch. To improve the accuracy of the detection algorithm, this paper injects small low-frequency reactive power mismatch to the output power of DG.

• Journal of IKEEE
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• v.28 no.1
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• pp.1-5
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• 2024

To improve the performance of DRAM, it is essential to reduce sensing failures caused by mismatch in SA. Unlike flip failures, delay failures can be degraded, especially when high-speed operation is required, making it a critical consideration in the design of next-generation memory. While conventional SA operates with all transistors starting amplification simultaneously, SDSA selectively activates only two transistors that output BLB, thus alleviating offset. In this paper, we validate the superior performance of SDSA in mitigating delay failures through simulations. It was confirmed that SDSA exhibits approximately a 90 % reduction in delay failures compared to conventional SA.

• Korean Journal of Remote Sensing
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• v.20 no.4
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• pp.227-234
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• 2004

The synchronization of Time Delay and Integration (TDI) against the temporal variation of osculating altitude in the operation of high resolution satellite imager was studied. The characteristics of osculating altitude variation was analyzed and its impact on the performance of TDI imger was also investigated. A practical ]me rate control method was proposed to compensate instantaneous TDI mismatch due to the osculating altitude variation, so that geometrical performance enhancement was achieved by the proposed method. This study is applicable to real satellite operation and can be useful for satellite image quality enhancement.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.538-541
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• 1998

This paper describes the development of 5.15ns 32kb asynchronous CMOS SRAM using 0.6.mu.m CMOS technology. The proposed high speed embedded SRAM is realized with optimized control circuit and sense amplifier at a power supply of 3V. Using proposed control circuit, the delay time from address input to wordline 'on' is reduced by 33% and mismatch-insensitive sense amplifier can sense a small difference of bit-line voltage fast and stably.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.183-187
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• 2003

The expression for the effects of an amplitude imbalance, a phase imbalance and a delay mismatch on the characteristics of a linearization loop in feedforward amplifiers is derived and analyzed. The simulation results are compared with the results obtained by means of using a commercial simulation tool and the exact agreement is reported.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.194-196
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• 2005

The command processor in satellite handles the capability of the process of command transmitted from ground station and deliver the processed data to on board computer in satellite. The command processor is consisted of redundant box to increase the reliability and availability of the capability. At each command processor, the processing time of each command processor is different, so the mismatch of processing time makes it difficult to timely synchronize the reception to on board computer and even will be became worse under the command processor's fault. To minimize the tine loss induced by the command processor's fault on board computer must analyze the time distribution of command propagation. This paper presents the logic of minimizing the delay error of command propagation the logic of analyzing the output of command processor.