• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.11
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• pp.859-865
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• 1991

The paper proposes a design of high-speed dynamic CMOS PLA (Programmable Logic Array) which performs stable circuit operation. The race problem which nay occur in a NOR-NOR implementation of PLA is free in the proposed dynamic CMOS PLA by delaying time between the clocks to the AND- and to the OR-planes. The delay element has the same structure as the product line of the longest delay in the AND p`ane. Therefore it is unnecessary to design the delay element or to calculate correct delay time. The correct delay generated by the delay element makes the dynamic CMOS PLA to perform correct and stable circuit operation. Theproposed dynamic CMOS PLA has few variation of switching delay with the increasing number of inputs or outputs in PLA. It is verified by SPICE circuit simulation that the proposed dynamic CMOS PLA has the better performance over existing dynamic CMOS PLA's.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.677-680
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• 2003

In this paper, the analysis of practical end-to-end delay in worst case is performed for distributed control system considering the implementation of the system. The control system delay is composed of the delay caused by multi-task scheduling of operating system, the delay caused by network communication, and the delay caused by the asynchronous between them. Through simulation tests based on CAN(Controller Area Network), the proposed end-to-end delay in worst case is validated. Additionally, online clock synchronization algorithm is proposed here for the control system. Through another simulation test, the online algorithm is proved to have better performance than offline one in the view of network bandwidth utilization.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.439-442
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• 2004

Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

• Journal of Advanced Marine Engineering and Technology
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• v.30 no.4
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• pp.505-513
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• 2006

A linear power amplifier is particularly emphasized on the system using a linear modulations, such as 16QAM and QPSK with pulse shaping. because intermodulation distortion which causes adjacent channel interference and co-channel interference is mostly generated in a nonlinear power amplifier. In this paper, parameters of a linearization loop, such as an amplitude imbalance a phase imbalance and a delay mismatch, are briefly analyzed to get a specific cancellation performance and linearization bandwidth. Experimental results are presented for IMT-2000 frequency band. The center frequency of the feedforward amplifier is 2140 MHz with 60 MHz bandwidth. When the average output power of feedforward amplifier is 20 Watt. the intermodulation cancellation performance is more than 21 dB. In this case, the output power of feedforward amplifier reduced 3.5 dB because of extra delay line loss and coupling loss. The feedforward amplifier efficiency is more than 7.2 % for multicarrier signals, 59 dBc for ACPR.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.1
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• pp.55-64
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• 1997

Spread Spectrum Communication is a core technique in CDMA system, but the problem for SS Communication schemes is synchronous method. There are DLL, Tau-dither, SO etc, in the synchronous method. But since there are analog operations, the settling is difficult and size is large. In this paper we realized Digital Delay Lock Loop (DDLL) and estimated it's performance through the Power line experiment.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.06a
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• pp.1176-1185
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• 2005

A linear power amplifier is particularly emphasized on the system using a linear modulations, such as 16QAM and QPSK with pulse shaping, because intermodulation distortion which causes adjacent channel interference and co-channel interference is mostly generated in a nonlinear power amplifier. In this paper, parameters of a linearization loop, such as an amplitude imbalance, a phase imbalance and a delay mismatch, are briefly analyzed to get a specific cancellation performance and linearization bandwidth. Experimental results are presented for IMT-2000 frequency band. The center frequency of the feedforward amplifier is 2140 MHz with 60 MHz bandwidth. When the average output power of feedforward amplifier is 20 Watt, the intermodulation cancellation performance is more than 21 dB. In this case, the output power of feedforward amplifier reduced 3.5 dB because of extra delay line loss and coupling loss. The feedforward amplifier efficiency is more than 7.2 % for multicarrier signals, 59 dBc for ACPR.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.601-604
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• 2002

In this paper, the timing do-skew modeling for a high speed logic tester channels is developed. The time delay of each channel in a logic tester are different from other channels and it can produce timing error in a test. To get the best timing accuracy in the test with a logic tester, the timing skew must be compensated. The timing skew of channels is due to the difference of time delay of pin-electronics devices composing channels and length of metal line placed on PCB. The expected timing difference of channels can be calculated according to the specifications of pin electronics devices and strip line modeling of PCB. With the calculated delay time, the timing skew compensation circuit has been designed. With the timing skew compensation circuit, the timing calibration of a logic tester can be peformed easily and automatically without other time measuring instruments. The calibration method can then be directly applied to logic testers in mass production lines.

• Journal of Navigation and Port Research
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• v.28 no.2
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• pp.149-154
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• 2004

A linear power amplifier is particularly emphasized on the system using a linear modulations, such as 16QAM and QPSK with pulse shaping, because intermodulation distortion which causes adjacent channel interference and co-channel interference is mostly generated in a nonlinear power amplifier. In this paper, parameters of a linearization loop, such as an amplitude imbalance, a phase imbalance and a delay mismatch, are briefly analyzed to get a specific cancellation performance and linearization bandwidth Experimental results are presented for IMT-2000 frequency band The center frequency of the feedforward amplifier is 2140MHz with 60MHz bandwidth When the average output power of feedforward amplifier is 20 Watt, the intermodulation cancellation performance is more than 28dB. In this case, the output power of feedforward amplifier reduced 3.5dB because of extra delay line loss and coupling loss. The feedforward amplifier efficiency is more than 7% for multicarrier signals.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.58-58
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• 2001

This paper shows a practical approach that is robust to the errors causing path-delay in mobile wireless location, and analyzes its performance by comparing with other methods. NLOS(non-line-of-sight) error and multipath are two big sources of positioning error in wireless location. Contrary to GPS(global positioning system), they result from the terrestrial propagation of a signal. Especially, since LOS(line-of-sight) path between a transceiver and a receiver is blocked by intermediate buildings and topography, NLOS causes a signal to be reflected and diffracted. This path-delay error is very localized, and so, it is not easy to be estimated and mitigated. To treat such localized error, therefore ...

• Current Optics and Photonics
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• v.3 no.5
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• pp.438-444
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• 2019

In this theoretical study, a line-defect photonic-crystal waveguide hosted in an annular photonic crystal was demonstrated to provide high-performance slow light with a wide band, low group-velocity dispersion, and a large normalized delay-bandwidth product. Combined with structural-parameter optimization and selective optofluid injection, the normalized delay-bandwidth product could be enhanced to a large value of 0.502 with a wide bandwidth of 58.4 nm in the optical-communication window, for a silicon-on-insulator structure. In addition, the group-velocity dispersion is on the order of $10^5$ ($ps^2/km$) in the slow-light region, which could be neglected while keeping the signal transmission unchanged.