• International Journal of Internet, Broadcasting and Communication
• /
• v.10 no.3
• /
• pp.109-114
• /
• 2018

In order to improve performance for the size of the BLPD, the CCL is used for the realization as the delay line. As realizing lower coupling coefficient and lower characteristic impedance, the CCL has good performance of the phase delay. The CCL is applied as the compact BLPD with optimized coupling factor and matched impedance because the lower coupling coefficient and lower characteristic impedance are increased the size and the loss, respectively. Designed BLPD using the CCL has the size of $0.13{\lambda}_g{\times}0.13{\lambda}_g$ and the size-reduction ratio of fabricated BLPD using the CCL has 58.5% ($21.08{\times}21.40mm^2$). Also, fabricated BLPD is measured the insertion loss of 3.16dB at the center frequency of 1.78GHz and the 20dB bandwidth is 9.58%. Differenced magnitude and phase between threw port and coupled port are measured 0.1dB and $89.9^{\circ}$, respectively. These performances are almost same compared with the conventional BLPD. Suggested application of the CCL can be used various devices and circuits for the size-reduction.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.2
• /
• pp.7-13
• /
• 2011

This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

• Proceedings of the KIEE Conference
• /
• 2000.07d
• /
• pp.2404-2406
• /
• 2000

Chua's circuit is a simple electronic network which exhibits a variety of bifurcation and attractors. The circuit consists of two capacitors, an inductor, a linear resistor, and a nonlinear resistor. In this paper, a transmitter and a receiver using two identical Chua's circuits are proposed and synchronizations of a T or ${\pi}$ type power line are investigated. Since the synchronization of the power line system is impossible by coupled synchronization, theory having both the drive-response and the coupled synchronization is proposed. As a result, the chaos synchronization has delay characteristics in the power line transmission system caused by the line parameters L and C

• Journal of Advanced Navigation Technology
• /
• v.7 no.2
• /
• pp.141-148
• /
• 2003

This paper presents and compares several techniques that detect the symbol rate of unknown received signal. Symbol rate is detected from the power spectral density of the circuits such as the delay and multiplier circuit, the square law circuit, and analytic signal, etc. As a result of discrete Fourier transform of the output signals of these circuits, a lot of spectral lines and some peaks appear in frequency domain and the position of first peak is corresponding to the symbol rate. If a spectral line on the frequency that is not located in symbol rate is larger than the first peak, the symbol rate is erroneously detected. Thus, the ratio between the value of first peak and the highest side spectral line is used for the measure of the performance of symbol rate detector. For the MPSK modulation, the analytic signal method shows better performance than the delay and multiplier and square law circuits when the received signal power is lager than -20dB. It is also noted that the delay and multiplier circuit is not able to detect the symbol rate for the QAM modulation.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.19 no.1
• /
• pp.1-10
• /
• 2024

The radio propagation characteristics of the 6, 10, and 17 GHz frequency bands in multiple paths in an indoor lobby environment were analyzed. The line-of-sight (LOS) and non-LOS (NLOS) paths were measured from a distance of 2-16 m (0.5 m intervals) from the transmitting to the receiving antenna positions. For basic transmission losses, three parameters were compared using the floating intercept path loss model corresponding to the path. For a root mean square delay spread, the measurement results were compared for cumulative probabilities of 10, 50, and 90%. Propagation loss and propagation delay occurred in all measured frequencies owing to the existence of pillars and an unusual lobby structure. Thus, a measurement scenario for an indoor lobby environment and the provision of standard measurement data was proposed. The results may facilitate research on the radio propagation characteristics of 5G and millimeter-wave bands in indoor lobby environments with various structures.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.26 no.2
• /
• pp.213-217
• /
• 2015

Microwave Photonic(MWP) filters capable of use a bandpass filter or a notch filter with large bandwidth have been proposed. 4-lines${\times}$2-bit fiber-optic delay lines with a unit time-delay difference of 50 ps were experimentally realized. By changing the time-delay difference and the coefficients of microwave-modulated optical signals, the bandpass and notch filters were implemented and characterized.

• Progress in Superconductivity
• /
• v.9 no.2
• /
• pp.157-161
• /
• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
• /
• 2002.11a
• /
• pp.130-136
• /
• 2002

Device makers want to make higher density chips as devices shrink, especially WSix poly stack down is one of the key issues. However, EPD (End Point Detection) time delay was happened in DPS+ poly chamber which is a barrier to achieve device shrink because EPD time delay killed test pattern and next generation device. To investigate the EPD time delay, a test was done with patterned wafers. This experimental was carried out combined with OES(Optical Emission Spectroscopy) and SEM (Scanning Electron Microscopy). OES was used to find corrected wavelength in WSix stack down gate etching. SEM was used to confirm WSix gate profile and gate oxide damage. Through the experiment, a new wavelength (252nm) line of plasma is selected for DPS+ chamber to call correct EPD in WSix stack down gate etching for current device and next generation device.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 1993.10a
• /
• pp.458-461
• /
• 1993

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.6
• /
• pp.681-689
• /
• 2010

We will demonstrate a novel topology for the feedforward amplifier. This amplifier does not use a delay element thus providing an efficiency enhancement and a size reduction by employing a distributed element negative group delay circuit. The insertion loss of the delay element in the conventional feedforward amplifier seriously degrades the efficiency. Usually, a high power co-axial cable or a delay line filter is utilized for a low loss, but the insertion loss, cost and size of the delay element still acts as a bottleneck. The proposed negative group delay circuit removes the necessity of the delay element required for a broadband signal suppression loop. With the fabricated 2-stage distributed element negative group delay circuit with -9 ns of total group delay, a 0.2 dB of insertion loss, and a 30 MHz of bandwidth for a wideband code division multiple access downlink band, the feedforward amplifier with the proposed topology experimentally achieved a 19.4 % power added efficiency and a -53.2 dBc adjacent channel leakage ratio with a 44 dBm average output power.