• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2828-2835
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• 1996

In this paper we propose a new shaping algorithm which can control the shaping delay and the output buffer size based on the leaky bucket counter with a threshold value. This paper assumes that input traffic of the proposed shaping algorithm is the worst case traffic tolerated by the continuous leaky bucket algorithm and claracterizes traffic patterns that can depart from our shaping algorithm. We also compare shaping delay and output buffer size of the proposed algorithm with the existing shaping algorithm without a threshold value. Our results show that the proposed shaping algorithm can easily manage the shaping delay and output buffer size than any other mechanism.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.909-912
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• 1998

In this paper, a new connection admission controller using neural network is presented. The controller measures traffic flow, cell loss rate, and cell delay periodically. Using those measured information, it learns the distributions of traffics of each traffic. Also the proposed controller is able to measure and manage the delays that source traffics experience through the network by using DWRR multiplexer with buffers dedicated to each traffic source. Experimental result show that the heterogeneous traffic sources with various QoS requirement.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.2
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• pp.181-186
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• 1998

This paper presents multiplexing structures to provide various subscriber interfaces in an ATM switching system with a high speed internal link, and analyzes the schemes in terms of a mean cell delay and a buffer sin. And we proposed a buffer management strategy to minimize a cell loss and accommodate new ATM transfer capabilities.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.11
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• pp.106-115
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• 1996

In this paper, the method using virtual scheduling suggested algorithm (VSSA) is suggested by considering cell delay variation and token rate of leaky bucket. This method is compared with virtual scheduling algorithm (VSA) and virtual scheduling algorithm with no tolerance excessive peak cell rate. As a result, the research shows that the usage parameter control using vSSA makes quality of service better than the usage parameter control using vSA or VSANT does because the suggested method reduces the violated cell probability of conformed peak cell rate and intentionally excessive peak cell rate.

• ETRI Journal
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• v.17 no.1
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• pp.23-36
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• 1995

We present a performance evaluation model of cell reassembly mechanism in an ATM switching system. An ATM switching system may be designed so that communications between processors of its control part can be performed via its switching network rather than a separate inter-processor communications network. In such a system, there should be interface to convert inter-processor communication traffic from message format to cell format and vice versa, that is, mechanisms to perform the segmentation and reassembly sublayer. In this paper, we employ a continuous-time Markov chain for the performance evaluation model of cell reassembly mechanism with individual buffering, judicially defining the states of the mechanism. Performance measures such as message loss probability and average reassembly delay are obtained in closed forms. Some numerical illustrations are given for the performance analysis and dimensioning of the cell reassembly mechanism.

• International journal of advanced smart convergence
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• v.13 no.1
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• pp.1-11
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• 2024

Cognitive small cell networks, consisting of macro-cells and small cells, are foreseen as a promising candidate solution to address 5G spectrum scarcity. Recently, many technological issues (such as spectrum sensing, spectrum sharing) related to cognitive small cell networks have been studied, but the common control channel (CCC) establishment problem has been ignored. CCC is an indispensable medium for control message exchange that could have a huge significant on transmitter-receiver handshake, channel access negotiation, topology change, and routing information updates, etc. Therefore, establishing CCC in cognitive small cell networks is a challenging problem. In this paper, we propose a potential game theory-based approach for CCC establishment in cognitive radio networks. We design a utility function and demonstrate that it is an exact potential game with a pure Nash equilibrium. To maintain the common control channel list (CCL), we develop a CCC update algorithm. The simulation results demonstrate that the proposed approach has good convergence. On the other hand, it exhibits good delay and overhead of all networks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.7-13
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• 2011

This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.6
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• pp.1480-1489
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• 1996

In ATM networks there are two methods in traffic control as schemes advancing the quality of service. One is reactive control after congestion and the other which is generally recommended, is preventive control before congestion, including connection admission control on call leel and usage parameter control, network parameter control, priority control and congestion control on cell level. In particular, usage parameter control is required for restricting the peak cell rate of bursy tracffic to the parameter negotiated at call set-up phase since the peak cell rate significantly influences the network quality of service. The scheme for progressing quality of service by usage parameter control is themethod using VSA(Virtual Scheduling Algorlithm) recommended ITU-T. The method using VSSA(Virtual Scheduling Suggested Algorlithm) in this paper is suggested by considering cell delay variation and token rate of leaky bucket, compared VSA and VSANT(Virtual Scheduling Algolithm with No Tolerance) with VSSA which polices violated cell probability of conformed peak cell rate and intentionally excessive peak cell rate. VSSA method using IPP(Interruped Poisson Process) model of input traffic source showed more quality of service than VSA and VSANT methods as usage parameter control because the suggested method reduced the violated cell probability of contformed peak cell rate and intentionally excessive peak cell rate.

• Korean Journal of Construction Engineering and Management
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• v.12 no.6
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• pp.31-41
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• 2011

Since the cases of time extension have continuously transpired in the public construction project, the potential of economical loss and claims is increasing because the concerned parties such as an owner or a contractor have not properly performed their own responsibility for time extension. One of the main reasons is that the present planning and scheduling do not support the method to apportion the proper responsibility to the right party. This problem has repeatedly led to time extension and made it difficult for the concerned parties to perform the responsibility for time extension. In order to overcome this problem, a framework of delay administration is required as the method to apportion the proper responsibility to the right party. To solve this problem, this paper aimed to develop the conceptual model and prototype system as the practical method to administrate delay causation. Furthermore, the verification result for the reliability and applicability throughout the case studies on real construction projects shows that the conceptual model and prototype system developed would help efficiently to administrate the delay causation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.38-47
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• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.