• Electrical & Electronic Materials
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• v.10 no.8
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• pp.800-806
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• 1997

The behavior of de levels in rapid thermal annealed Fe-doped semi-insulating InP(100) was studied by photoinduced current transient spectrocopy(PICTS). In bulk InP, T2(Ec-0.24 eV), T3(Ec-0.30 eV) and T5(Ec-0.62 eV) traps were observed. After annealing the T2 trap was annihilated at 20$0^{\circ}C$ and recreated at 35$0^{\circ}C$. T3 trap was not affected below 40$0^{\circ}C$. With increasing temperature the concentration of T5 trap reduced and it was annihilated at 30$0^{\circ}C$. However the T1(Ec-0.16 eV) and T4(Ec-0.42 eV) traps were began to appear at 40$0^{\circ}C$and these concentrations were increased with annealing temperature. The T1 and T4 traps seem to be related to the isolated phosphorus vacancy( $V_{p}$) and $V_{p}$-indium antisite( $V_{p}$- $P_{in}$ ) or $V_{p}$-indium interstitial( $V_{p}$-I $n_{I}$) respectiely.respectiely.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.150-153
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• 2004

본 논문에서는 780 nm 고출력 레이저 다이오드의 신뢰성을 향상시키기 위하여 DLTS(deep level transient spectroscopy)을 이용하여 MOCVD(metalorganic chemical vapor deposition) 성장 조건 변화에 따른 $Al_{0.48}Ga_{0.52}As$와 $Al_{0.1}Ga_{0.9}As$ 물질에서의 깊은준위(deep level)의 거동을 조사하였다. DLTS 측정결과, MOCVD로 성장된 막에서만 나타나는 결함(defect)으로 추정되는 trap A(0.3 eV), DX center로 알려진 trap B, 갈륨(Ga) vacancy와 산소(O2) 원자의 복합체(complex)에 의한 결함인 trap D(0.6 eV) 및 EL2 라고 불리우는 trap E(0.9 eV)의 네 가지 깊은준위들이 관측되었고, 성장 조건의 변화에 따라 깊은 준위들의 농도가 감소하는 것을 관측함으로써 최적 성장 조건을 찾을 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.191.2-191.2
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• 2013

The negative photoconductivity was frequently observed in some semiconductors. It was known that the origin of the negative photoresponse from ZnO is molecular chemisorption or the charging effect of nanoparticles in bulk matrix. However, the origin of the negative photoresponse of thin film was not still clear. One of possible explanation is due to the deep level trap scheme, which describes the origin of the negative photoresponse via defect state under illumination of light. However, the defect states below Fermi level have high capture rate by Coulomb effect, so that these states are usually filled by electrons if the defect states have donor-like character. Therefore the condition which the defect states located in below Fermi level should be partially filled by electrons make more difficult to understand of mechanism of the negative photoresponse. In this study, n-ZnO/p-Si heterojunction diodes were fabricated by UHV RF magnetron sputter. Then, some diodes show the negative photoresponse under ultra-violet light illumination. The defect state of the ZnO was analyzed by photoluminescence and deep level transient spectroscopy. To interpret the negative photoconductivity, band diagram was simulated by using SCAPS program.

• Electrical & Electronic Materials
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• v.7 no.3
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• pp.213-219
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• 1994

Cu compensated Si doped GaAs (GaAs :Si:Cu has been chosen as the switch material. The GaAs material has been characterized by DLTS(Deep Level Transient Spectroscopy) technique and the obtained data were used in the computer simulation. Simulation studies are performed on several GaAs switch systems, composed of different densities of Cu, to investigate the influence of deep traps in the switch systems. The computed results demonstrates important aspect of the switch, the existence of two stable states and fast optical quenching. An important parameter optimum Cu density for the switch are also determined.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.96-103
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• 1994

The GaAs epilayer was grown at low temperature (LT. 250.deg. C) by molecular beam epitaxy. The properties of the LTT GaAs, before and after Rapid Thermal Annealing(RTA), were analyzed by Reflection of High Energy Electron Diffraction (RHEED), Double Crystal X-ray(DCX), Raman spectroscopy, PL and Photo-Induced Current Transient Spectroscopy (PICTS). The LT GaAs before RTA, was analyzed by RHEED and DCX, with a result of an improved surface morphology under a relatively As-rich(As/Ga ratio :28) condition, and of an increased lattics parameter of 1.1 1.7% in comparison with a GaAs substrate. However DCX and Raman spectroscopy revealed that the expanded lattics parameter and the crystallinity of LT GaAs could be recovered after RTA. On the other hand, PL spectra indicated that LT GaAs after RTA showed low optical sensitivity unlike High Temperature(HT) GaAs, and that its surface morphology and crystallinity were corresponded with those of HT GaAs. Finally PICTS spectra proved the fact that low sensitivity of LT GaAs was due to the deep level defects (Ec-0.85eV) which were strogly formed by raising RTA temperature to 750.deg. C.

• Korean Journal of Materials Research
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• v.34 no.2
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• pp.111-115
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• 2024

Silicon carbide (SiC) has emerged as a promising material for next-generation power semiconductor materials, due to its high thermal conductivity and high critical electric field (~3 MV/cm) with a wide bandgap of 3.3 eV. This permits SiC devices to operate at lower on-resistance and higher breakdown voltage. However, to improve device performance, advanced research is still needed to reduce point defects in the SiC epitaxial layer. This work investigated the electrical characteristics and defect properties using DLTS analysis. Four deep level defects generated by the implantation process and during epitaxial layer growth were detected. Trap parameters such as energy level, capture-cross section, trap density were obtained from an Arrhenius plot. To investigate the impact of defects on the device, a 2D TCAD simulation was conducted using the same device structure, and the extracted defect parameters were added to confirm electrical characteristics. The degradation of device performance such as an increase in on-resistance by adding trap parameters was confirmed.

• Proceedings of the Materials Research Society of Korea Conference
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• 1995.11a
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• pp.23-24
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• 1995

기존의 웨이퍼 박막속에 절연박막이 삽입된 SOI(Silicon On Insulator) 웨이퍼 구조와 관련한 반도체 기판 재료가 커다른 관심을 끌어 왔으나, SOI 평가기술은 아직까지 체계적으로 확립된 것이 없으며, DLTS(Deep Level Transient Spectroscopy) 등을 이용한 전기적 평가는 거의 이루어지지 않은 상태이다. 본 연구에서는 직접접합된 웨이퍼를 약 10um내외의 활성화층을 형성시킨 6인치 P-형 SOI 웨이퍼를 제작하여 DLTS로 측정, 평가를 하였고, DLTS 측정후 관찰될 수 있는 에어지 트랩(Energy Trap)과 후속 열처리에서의 트랩의 변화등을 관찰하여, 후속 열처리조건에 따른 접합된 SOI 웨이퍼 계면의 안정화된 조건을 확보하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.460-460
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• 2013

본 연구는 Si (111) 기판위에 Ga 분자선량을 변화시켜 GaN 박막을 molecular beam epitaxy 법으로 성장하고, Schottky 장벽 다이오드를 제작한 후에 deep level transient spectroscopy (DLTS) 법을 통하여 깊은 준위 결함에 대하여 조사하였다. 성장 시 Ga 분자선량은, 그리고 Torr로 달리하여 V/III 비율을 변화시켰고, Schottky 장벽 다이오드 제작을 위하여 e-beam evaporator를 사용하여 metal을 증착하였다. Schottky 접촉에는 Ni (20 nm)/Au (100 nm)를 증착하였고, ohmic 접촉에는 Ti (20 nm)/Au (100 nm)를 증착하고 I-V, C-V 그리고 DLTS를 측정하였다. DLTS 신호를 통해 GaN 박막 성장 과정에서 형성되는 깊은 결함의 종류를 확인하였으며, 열처리 등의 처리 및 측정 조건변화에 따른 결함의 거동과 종류 및 원인에 대하여 분석 설명하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.5
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• pp.365-370
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• 2000

Schottky contacts on n-In$\_$0.53//Ga$\_$0.47//As have been made by metal deposition on substrates cooled to a temperature of 77K. The current-voltage and capacitance-voltage characteristics showed that the Schottky diodes formed at low temperature had a much improved barrier height compared to those formed at room temperature. The Schottky barrier height ø$\_$B/ was found to be increased from 0.2eV to 0.6eV with Ag metal. The saturation current density of the low temperature diode was about 4 orders smaller than for the room temperature diode. A current transport mechanism dominated by thermionic emission over the barrier for the low temperature diode was found from current-voltage-temperature measurement. Deep level transient spectroscopy studies exhibited a bulk electron trap at E$\_$c/-0.23eV. The low temperature process appears to reduce metal induced surface damage and may form an MIS (metal-insulator-semiconductor)-like structure at the interface.

• Electrical & Electronic Materials
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• v.3 no.3
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• pp.195-204
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• 1990

본 논문에서는 컴퓨터를 근본으로 한 Deep Level Transient Spectroscopy (DLTS) 장치를 구성하고 이를 이용하여 P형 Si MOS 캐패시터의 Si- $SiO_{2}$ 계면상태를 측정하여 트랩의 활성화에너지와 포획단면적 그리고 계면트랩밀도를 조사하였다. 실리콘 band gap내에 연속적으로 분포하고 있는 계면트랩을 상세히 고찰하기 위해 quiescent 전압의 위치를 변화시키면서 0.1volt의 미소한 펄스를 MOS에 주입하여 그 각각이 분리된 트랩이라고 생각되는 매우 좁은 에너지 영역에서 나오는 DLTS신호를 측정하였다. 또한 quiescent 전압의 위치, 주입펄스전압의 진폭 그리고 rate window의 선택이 DLTS 신호에 미치는 영향 등을 조사하였다. 측정결과, 계면트랩의 활성화에너지는 가전자대로 부터 0.16-0.45eV이고 포획단면적은 1.3*$10^{-19}$~3.2*$10^{-15}$$cm^{2}$, 계면트랩밀도는 1.8*$10^{10}$ ~ 2.5*$10^{11}$$cm^{-2}$e$V^{-1}$로 측정되었다.