• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.5
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• pp.84-93
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• 2000

The conventional fractal decoding was implemented to IFS(iterated function system) for every range regions But a part of the range regions can be decoded without the iteration and there is a data dependence regions In order to decode $R{\times}R$ range blocks, It needs $2R{\times}2R$ domain blocks This decoding can be analyzed to the dependence graph The vertex of the graph represents the range blocks, and the vertex is classified into the vertex of the range and domain The edge indicates that the vertex is referred to the other vertices The in-degree and the out-degree are defined to the number of the edge that is entered and exited, respectively The proposed method is analyzed by a dependence graph to the fractal code, and the decoding order is recomposed by the information of the out-degree That is, If the out-degree of the vertex is zero, then this vertex can be used to the vertex with data dependence Thus, the proposed method can extend the data dependence regions by the recomposition of the decoding order As a result, the Iterated regions are minimized without loss of the image quality or PSNR(peak signal-to-noise ratio), Therefore, it can be a fast decoding by the reducing to the computational complexity for IFS in the fractal Image decoding.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.4
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• pp.876-884
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• 2014

A hardware design of LDPC decoder which is based on the improved normalized min-sum(INMS) decoding algorithm is described in this paper. The designed LDPC decoder supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. The decoding function unit(DFU) which is a main arithmetic block is implemented using sign-magnitude(SM) arithmetic and INMS decoding algorithm to optimize hardware complexity and decoding performance. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 100 MHz clock has 284,409 gates and RAM of 62,976 bits, and it is verified by FPGA implementation. The estimated performance depending on code rate and block length is about 82~218 Mbps at 100 MHz@1.8V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3C
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• pp.322-328
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• 2009

This paper proposes new simplified sum-product (SSP) decoding algorithm to improve BER performance for low-density parity-check codes. The proposed SSP algorithm can replace multiplications and divisions with additions and subtractions without extra computations. In addition, the proposed SSP algorithm can simplify both the In[tanh(x)] and tanh-1 [exp(x)] by using two quantization tables which can reduce tremendous computational complexity. Moreover, the simulation results show that the proposed SSP algorithm can improve about $0.3\;{\sim}\;0.8\;dB$ of BER performance compared with the existing modified sum-product algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.984-995
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• 1996

Data errors according to the various noises caused in the satellite communication links are corrected by the Viterbi decoding algorithm which has extreme error correcting capability. In this paper, we designed and implemented a convolutional encoder and Viterbi decoder ASIC which is used to encode the input data at the transmit side and correct the errors of the received data at the receive side for use in the VSAT communication system. And this chip may be used in any BPSK, QPSK, or OQPSK transmission system. The ambiguity resolver corrects PSK modem ambiguities by delaying, interting, and/or exchanging code symbol to restore their original sequence and polarity. In case of previous decoding system, ambiguity state(AS) of data is resolved by external control logic and extra redundancy data are needed to resolve AS. But, by adopting decoder proposed in this paper, As of data is resolved automatically by internal logic of decoder in case of continuous mode, and by external As line withoug extra redudancy data in burst mode case. So, decoding parts are simple in continuous mode and transmission efficiency is increased in bust mode. The features of this chip are full duplex operation with independent transmit and receive control and clocks, start/stop inputs for use in burst mode systems, loopback function to verify encoder and decoder, and internal or external control to resolve ambinguity state. For verification of the function and performance of a fabricated ASIC chip, we equiped this chip in the Central and Remote Earth Station of VSAT system, and did the performance test using the commerical INTELSAT VII under the real satellite link environmens. The results of test were demonstrated the superiority of performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8C
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• pp.775-781
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• 2007

In this paper, a modified PTS(Partial Transmit Sequences) technique that uses erasure decoding of RS (Reed-Solomon) codes is presented. At the transmitter, some check symbols in a RS codeword partitioned into subblocks are phase-rotated by phase factors. The receiver decodes received codewords by regarding the phase-rotated check symbols as erasures. Hence, this technique does not need to transmit the side information about the phase factors chosen at the transmitter. The complexity of the receiver is also reduced since the estimation process for the phase factors is not required in the receiver. There is no performance degradation due to the transmission error of the side information or the estimation error of the phase factors. To evaluate the performance of the proposed PTS technique, the CCDF(Complementary Cumulative Distribution Function) of PAPR and the BER(Bit Error Rate) are compared with those of the conventional PTS techniques.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.798-801
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• 2010

This paper describes an efficient architecture for LDPC(Low-Density Parity Check) decoder, which supports three block lengths (648, 1,296, 1,944) of IEEE 802.11n standard. To minimize hardware complexity, the min-sum algorithm and block-serial layered structure are adopted in DFU(Decoding Function Unit) which is a main functional block in LDPC decoder. The optimized H-ROM structure for multi block lengths reduces the ROM size by 42% as compared to the conventional method. Also, pipelined memory read/write scheme for inter-layer DFU operations is proposed for an optimized operation of LDPC decoder.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.1
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• pp.452-472
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• 2019

Most existing wavelet-based multiplicative watermarking methods are affected by geometric attacks to a certain extent. A serious limitation of wavelet-based multiplicative watermarking is its sensitivity to rotation, scaling, and translation. In this study, we propose an image watermarking method by using dual-tree complex wavelet transform with a multi-objective optimization approach. We embed the watermark information into an image region with a high entropy value via a multiplicative strategy. The major contribution of this work is that the trade-off between imperceptibility and robustness is simply solved by using the multi-objective optimization approach, which applies the watermark error probability and an image quality metric to establish a multi-objective optimization function. In this manner, the optimal embedding factor obtained by solving the multi-objective function effectively controls watermark strength. For watermark decoding, we adopt a maximum likelihood decision criterion. Finally, we evaluate the performance of the proposed method by conducting simulations on benchmark test images. Experiment results demonstrate the imperceptibility of the proposed method and its robustness against various attacks, including additive white Gaussian noise, JPEG compression, scaling, rotation, and combined attacks.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.8
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• pp.7-14
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• 2011

In this paper we studied a conventional system and propose a new decoding scheme for Space-time Frequency Code with Interleaved System. We also addressed the quasi orthogonal function with Jacket matrices in modern 3GPP LTE uplinked advance system. We also introduce the Partial Interference Cancellation (PIC) group decoding which provides a framework to adjust the complexity-performance tradeoff by choosing the sizes of the information symbols groups.

• Journal of Korea Multimedia Society
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• v.2 no.1
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• pp.38-46
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• 1999

In this paper, the fractal image compression using the minimizing method of domain region is proposed. It is minimize to domain regions in the process of decoding. Since the conventional fractal decoding applies to IFS(iterative function system) for the total range blocks of the decoded image, its computational complexity is a vast amount. In order to improve this using the number of the referenced times to the domain blocks for the each range blocks, a classification method which divides necessary and unnecessary regions for IFS is suggested. If necessary regions for IFS are reduced, the computational complexity is reduced. The proposed method is to define the minimum domain region that a necessary region for IFS is minimized in the encoding algorithms. That is, a searched region of the domain is limited to the range regions that is similar with the domain regions. So, the domain region is more overlapped. Therefore, there is not influence on image quality or PSNR(peak signal-to-noise ratio). And it can be a fast decoding by reduce the computational complexity for IFS in fractal image decoding.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.92-100
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• 2009

In this paper, we analyze the hardware architecture of Low Density Parity Check (LDPC) decoder using Log Likelihood Ration-Belief Propagation (LLR-BP) decoding algorithm. Various design issues that affect the decoding performance and the hardware complexity are discussed and the tradeoffs between the hardware complexity and the performance are analyzed. The message data for passing error probability is quantized to 7 bits and among them the fractional part is 4 bits. To maintain the decoding performance, the integer and fractional parts for the intrinsic information is 2 bits and 4 bits respectively. We discuss the alternate implementation of $\Psi$(x) function using piecewise linear approximation. Also, we improve the hardware complexity and the decoding time by applying overlapped scheduling.