• Journal of the Korea Society of Computer and Information
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• v.11 no.3
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• pp.161-166
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• 2006

In this paper, CPLD low power technology mapping using reuse module selection under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.15-26
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• 2005

In this paper, we propose an efficient $GF(2^m)$ multi-segment multiplier architecture and study its application to elliptic curve cryptography processors. The multi-segment based ECC datapath has a very small combinational multiplier to compute partial products, most of its internal data buses are word-sized, and it has only a single m bit multiplexer and a single m bit register. Hence, the resource requirements of the proposed ECC datapath can be minimized as the segment number increases and word-size is decreased. Hence, as compared to the ECC processor based on digit-serial multiplication, the proposed ECC datapath is more efficient in resource usage. The resource requirement of ECC Processor implementation depends not only on the number of basic hardware components but also on the complexity of interconnection among them. To show the realistic area efficiency of proposed ECC processors, we implemented both the ECC processors based on the proposed multi-segment multiplication and digit serial multiplication and compared their FPGA resource usages. The experimental results show that the Proposed multi-segment multiplication method allows to implement ECC coprocessors, requiring about half of FPGA resources as compared to digit serial multiplication.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.200-203
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• 2000

In this paper, we describes the design of a CPU compatible with ARM9 processor. The CPU is fully synthesizable and described in Verilog-XL. Starting from the synthesizable ARM7 compatible CPU we developed earlier, we modified its pipeline to five stages. For this we first partition the behaviors of each instruction into five stage pipeline operations. Then we designed the controller and the datapath considering the forwarding or interlock schemes. Finally the compatibility of the designed CPU is verified by comparing the results of every instruction executed in test programs with those of the reference simulator developed for the ARM7 compatible CPU.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.985-988
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• 1999

This paper describes the architecture and the IC implementation of a Direct Digital Frequency Synthesizer (DDFS). That is based on an angle rotation algorithm (CORDIC). It is shown that the architecture can be implemented as a multipliers, feedfoward, and easily pipelineable datapath. A prototype IC has been designed, fabricated in 0.35${\mu}{\textrm}{m}$ SAMSUNG KG90 Library.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.931-933
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• 2004

In a SoC environment, asynchronous design techniques offer solutions for problems of synchronous design techniques. Asynchronous FIFOs have the advantages of easier interconnection methods and higher throughput than synchronous ones. Low latency and high throughput are two imp ortant standards in asynchronous FIFOs. We present low latency asynchronous FIFO in the paper, which optimizes GasP[6]. Pre-layout of HSPICE simulations of a 8-stage FIFO on 1-bit datapath using Anam's 0.25$\mu\textrm{m}$ technology indicates 17% lower latency than GasP.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.444-453
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• 1997

This paper presents the prototype design of hardware/software cosynthesis system for pipelined application-specific instruction processors. Taking application programs in VHDL as inputs, the proposed system generates a pipelined instruction-set processor and the instruction sequences running on the generated machine. The design space of datapath and controller is defined by the architectural templates embedded in the system. Generating the intyermediate code adequate for parallelism analysis and extraction, the system converts it into assembly codes. Experimental results show the effectiveness of the proposed system.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2196-2203
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• 1999

This paper describes the bus scheduling problem and register optimization method in datapath synthesis. Scheduling is process of operation allocation to control steps in order to minimize the cost function under the given circumstances. For that purpose, we propose some formulations to minimize the cost function for bus assignment to get an optimal and minimal cost function in hardware allocations. Especially, bus and register minimization technique are fully considered which are the essential topics in hardware allocation. Register scheduling is done after the operation and bus scheduling. Experiments are done with the DFG model of fifth-order digital ware filter to show its effectiveness. Structural integer programming formulations are used to solve the scheduling problems in order to get the optimal scheduling results in the integer linear programming environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.4
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• pp.424-432
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• 1992

This paper deals with the scheduling ploblems, which are the most important subtasks in High-level syntheses. IP(integer programming) formulations is used as the scheduling problem approach. This paper describes a new resource-constraints scheduling algorithm. We have concentrated our attentions on the multicycle operations and the structural pipelining, and we fully analyze the characteristics of operators to achieve the maximal performance and the maximal resource sharing. For experiment results, we choose the 5-th order digital wave filter as a benchmark and do the schedule, Finally, we can obtain near-optimal scheduling results.

• ETRI Journal
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• v.25 no.5
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• pp.305-314
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• 2003

In this paper, we present a soft IP compiler for the Reed-Solomon decoder that generates a fully synthesizable VHDL core exploiting characteristic parameters and design constraints that we newly classify for the soft IP. It produces a structural design with an estimable regular architecture based on a finite state machine with a datapath (FSMD). Since characteristic parameters provide different design points on the design space, using one of two simple procedures called the constructive search with area increment (CSAI) and constructive search with speed decrement (CSSD) for design space exploration, the core compiler makes it possible for an IP user to create the Reed-Solomon decoder with appropriate sub-architectures without synthesizing many models. Experimental results show that the IP compiler can apply to several industry standards.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.7
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• pp.520-534
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• 1991

This paper describes the design of an ALU and a shifter for RISC. The RISC datapath is designed to have a 4-stage pipeline and a 20 MHz operating frequency. The ALU makes use of the 32-bit BLC adder which has the characteristics of high speed ane regular structuer and executes the arithmetic instructions-addition and subtraction- and the logical instructions-AND, OR, and XOR. Additionally, multiplication is possible by iterative executions of step instructions to perform shift and add operations. The shifter is implemented by using the modified of funnel shifter. The shifter is able to perform the arithmetic andlogical shift instructions without maskiog. Moreover, it carries out data align operation which conforms to big endian byte address. The logical operation of the desinged ALU and the shifter were simulated using YSLOG and VLSIsim. SPICE simulation results using 1.2um double metal process parameters show that the ALU and shifter have a delay time of 15.9NS and 9.9NS, respectively. Therefore, the ALU and the shifter operates correctly above 20[ MHz ] click ferquency and are composed of about 7K and 15K teansistors, respectively.