• 전자통신동향분석
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• 제38권5호
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• pp.23-33
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• 2023

With the widespread demand from data-intensive tasks such as machine learning and large-scale databases, the amount of data processed in modern computing systems is increasing exponentially. Such data-intensive tasks require large amounts of memory to rapidly process and analyze massive data. However, existing computing system architectures face challenges when building large-scale memory owing to various structural issues such as CPU specifications. Moreover, large-scale memory may cause problems including memory overprovisioning. The Compute Express Link (CXL) allows computing nodes to use large amounts of memory while mitigating related problems. Hence, CXL is attracting great attention in industry and academia. We describe the overarching concepts underlying CXL and explore recent research trends in this technology.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.142-148
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• 2023

In this paper, we identify performance issues in executing compute kernels from PolyBench, which includes compute kernels that are the core computational units of various data-intensive workloads, such as deep learning and data-intensive applications, on Processing-in-Memory (PIM) devices. Therefore, using our in-house simulator, we measured and compared the various performance metrics of workloads based on traditional out-of-order and in-order processors with Processing-in-Memory-based systems. As a result, the PIM-based system improves performance compared to other computing models due to the short-term data reuse characteristic of computational kernels from PolyBench. However, some kernels perform poorly in PIM-based systems without a multi-layer cache hierarchy due to some kernel's long-term data reuse characteristics. Hence, our evaluation and analysis results suggest that further research should consider dynamic and workload pattern adaptive approaches to overcome performance degradation from computational kernels with long-term data reuse characteristics and hidden data locality.

• 한국콘텐츠학회논문지
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• 제11권12호
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• pp.597-610
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• 2011

데이터베이스 응용 프로그램 개발에서 데이터는 메모리 공간과 디스크 공간에 공존한다. 메모리 공간의 데이터를 조작하기 위하여 일반 프로그래밍 언어를 사용하고 디스크 공간의 데이터 조작을 위하여 SQL을 사용한다. 특히 메모리 데이터를 조작하기 위해 사용되는 절차적 언어는 SQL등의 선언적 언어보다 작성 및 유지보수가 어렵다. 이에 본 논문은 특수한 형태 즉, 트리 구조의 메모리 데이터는 선언적 언어인 SQL로 조작이 가능함을 보인다. 특히 UI (user interface)의 모델 데이터는 트리 구조로 표현 될 수 있기 때문에 예외적인 계산을 제외하고는 대부분의 메모리 데이터 조작은 SQL로 가능하다. 예외적인 계산은 도움 클래스 (helper class)로 처리하면 된다. 본 논문이 제시하는 SQL 메모리 데이터 조작은 예외적인 계산이 적은 데이터베이스 응용 프로그램 개발에 특히 적합하다.

• 정보처리학회논문지:소프트웨어 및 데이터공학
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• 제7권8호
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• pp.307-324
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• 2018

최근 순환 신경 망(Recurrent Neural Networks)은 시간에 대한 의존성을 고려한 구조를 통해 순차 데이터(Sequential data)의 예측 문제 해결에서 각광받고 있다. 하지만 순차 데이터의 시간 스텝이 늘어남에 따라 발생하는 그라디언트 소실(Gradients vanishing)이 문제로 대두되었다. 이를 해결하기 위해 장단기 기억 모델(Long Short-Term Memory)이 제안되었지만, 많은 데이터를 저장하고 장기간 보존하는 데에 한계가 있다. 따라서 순환 신경망과 메모리 요소(Memory component)를 활용한 학습 모델인 메모리-증대 신경망(Memory-Augmented Neural Networks)에 대한 연구가 최근 활발히 진행되고 있다. 본 논문에서는 딥 러닝(Deep Learning) 분야의 화두로 떠오른 메모리-증대 신경망 주요 모델들의 구조와 특징을 열거하고, 이를 활용한 최신 기법들과 향후 연구 방향을 제시한다.

• Journal of Information Technology Applications and Management
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• 제29권5호
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• pp.27-37
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• 2022

This study intends to link agricultural machine history data with related organizations or collect them through IoT sensors, receive input from agricultural machine users and managers, and analyze them through AI algorithms. Through this, the goal is to track and manage the history data throughout all stages of production, purchase, operation, and disposal of agricultural machinery. First, LSTM (Long Short-Term Memory) is used to estimate oil consumption and recommend maintenance from historical data of agricultural machines such as tractors and combines, and C-LSTM (Convolution Long Short-Term Memory) is used to diagnose and determine failures. Memory) to build a deep learning algorithm. Second, in order to collect historical data of agricultural machinery, IoT sensors including GPS module, gyro sensor, acceleration sensor, and temperature and humidity sensor are attached to agricultural machinery to automatically collect data. Third, event-type data such as agricultural machine production, purchase, and disposal are automatically collected from related organizations to design an interface that can integrate the entire life cycle history data and collect data through this.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.251-254
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• 1998

This paper suggests two data exchange protocols (DEPs) using shared memory. They support reliable data exchanges among components which are located in the same rack and use the same backplane bus and shared memory.

• International Journal of Internet, Broadcasting and Communication
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• 제10권4호
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• pp.6-11
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• 2018

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation.These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.185-196
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• 2002

MRAM(magnetic random access memory) is a promising candidate for a universal memory with non-volatile, fast operation speed and low power consumption. The simplest architecture of MRAM cell is a combination of MTJ(magnetic tunnel junction) as a data storage part and MOS transistor as a data selection part. This article will review the general development status of MRAM and discuss the issues. The key issues of MRAM technology as a future memory candidate are resistance control and low current operation for small enough device size. Switching issues are controllable with a choice of appropriate shape and fine patterning process. The control of fabrication is rather important to realize an actual memory device for MRAM technology.

• International journal of advanced smart convergence
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• 제6권1호
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• pp.39-43
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• 2017

As the industry grows, the amount of data grows exponentially, and data analysis using these serves as a predictable solution. As data size increases and processing speed increases, it has begun to be applied to new fields by combining artificial intelligence technology as well as simple big data analysis. In this paper, we propose a method to quickly apply a machine learning based algorithm through efficient resource allocation. The proposed algorithm allocates memory for each attribute. Learning Distinct of Attribute and allocating the right memory. In order to compare the performance of the proposed algorithm, we compared it with the existing K-means algorithm. As a result of measuring the execution time, the speed was improved.

• 대한임베디드공학회논문지
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• 제6권6호
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• pp.345-359
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• 2011

In high performance embedded systems, the use of multiple on-chip memories is an essential architectural feature for exploiting inherent parallelism in multimedia applications. This feature allows multiple data accesses to be executed in parallel. However, it remains difficult to effectively exploit of multiple on-chip memories. The successful use of this architecture strongly depends on how to efficiently detect and exploit memory parallelism in target applications. In this paper, we propose a technique based on a linear array access descriptor [1], which is generated from profiled data, to detect and exploit memory parallelism. The proposed technique tackles an array reorganization problem to maximize memory parallelism in multimedia applications. We present preliminary experiments applying the proposed technique onto a representative coarse grained reconfigurable array processor (CGRA) with multimedia kernel codes. Our experimental results demonstrate that our technique optimizes data placement by putting independent data on separate storage. The results exhibit 9.8% higher performance on average compared to the existing method.