• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.353-356
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• 2002

In this paper, we design an efficient, scalable one-dimensional discrete wavelet transform (1DDWT) filter using data reorder unit (DRU). At each level, the required hardware is optimized by sharing multipliers and adders because the input rate is reduced by a factor of two at each level due to decimation. The proposed architecture shows 100% hardware utilization by balancing hardware with input rate. Furthermore, sharing the coefficients of the highpass and the lowpass filters using the mirror filter property reduces the number of multipliers and adders by half. We designed a scalable DRU that efficiently reorders and feeds inputs to highpass and lowpass filters. The proposed DRU-based architecture is so regular and scalable that it can be easily extended to an arbitrary 1D DWT structure with M taps and J levels. Compared to other architectures, the proposed DWT filter shows efficiency in performance with relatively less hardware.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.139-140
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• 2008

지상라이다는 고정도의 3차원 영상을 제공하고 레이저 빔을 현장이나 대상물에 발사하여 짧은 시간에 수백만점의 3차원좌표를 기록할 수 있는 최신 측량장비로서 다양한 응용분야에서 두각을 나타내고 있다. 본 연구에서는 지상라이다를 이용한 건축물의 3자윈 자동 윤곽선 추출을 다룬다. 지상라이다는 건축물의 3차원 윤곽선을 신속하게 추출할 수 있지만 지상기반 시스템이므로 여러 가지 장애물 때문에 건국물의 하단부에서는 추출이 쉽지 않다. 기존 항공라이다를 이용한 알고리즘에서는 사진의 색상차나 모폴로지 특성에 의존하여 범위를 제한하고, 이를 기반으로 윤곽선을 추출하였다. 하지만 지상라이다의 경우 항공라이다에 비해 분해능이 월등히 높다. 또한, 지상라이다는 지상에서 측정하기 때문에 항공라이다에서 어려운 건축물의 측면이나 정면도 윤곽선 추출이 가능하기 때문에 본 논문에서는 사진을 이용하지 않고 전처리를 하지 않은 데이터를 직접 이용하여 건물의 정면 윤곽선을 추출하는 것을 제안한다. 건물의 크기와 데이터 수 즉, 라이다로 측정한 포인트 수를 고려한 효율적인 Decimation방법을 제안하고 또한, Decimation된 데이터이서 지역적으로 제일 큰 값과 작은 값을 찾아낸다. 그 중 많이 벗어난 점을 편차를 이용하여 제거한다. 이렇게 찾아낸 건축물의 외곽점들을 이어 만든 윤곽선을 최종적으로 보간하여 좀 더 현실과 가까운 윤곽선 추출 방법을 제안한다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.12
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• pp.155-160
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• 2003

Owing to the advances in ADC and DSP technologies, signals in If band, which once had to be processed in analog technology, can new be digitally processed. This is referred to as "Digital IF" or "Digital Radio", which is a preliminary stage of SDR. Applying the digital radio technology to a multi-carrier receiver design, a processing gain is generated through an over-sampling of input data. In the digital receiver, decimation is performed for reducing the computational complexity CIC and half band filter is used together with the decimation as an anti-alising filter. The CIC filter, however, should introduce the roll-off phenomenon in the passband, which causes the receiving performance to be considerably degraded due to the distorted Passband flatness of receiving filter. In this paper, we designed a CIC roll-off compensation filter for W-CDMA digital receiver. The performance of the proposed compensation filter is confirmed through computer simulations in such a way that the BER is minimized by compensating the roll-off characteristics.off characteristics.

• The Journal of the Acoustical Society of Korea
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• v.28 no.1
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• pp.1-9
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• 2009

This paper deals with the realization of multi-channel live karaoke. In this study, 6-channel MP3 decoding and tempo/key scaling was operated in real time by using the TMS320C6713 DSP, which is 32 bit floating-point DSP made by TI Co. The 6 channel consists of front L/R instrument, rear L/R instrument, melody, and woofer. In case of the 4 channel, rear L/R instrument can be replaced with drum L/R channel. And the final output data is generated as adjusted to a 5.1 channel speaker. The SOLA algorithm was applied for tempo scaling, and key scaling was done with interpolation and decimation in the time domain. Drum channel was excluded in key scaling by separating instruments into drums and non-drums, and in processing SOLA, high-quality tempo scaling was made possible by differentiating SOLA frame size, which was optimized for real-time process. The use of 6 channels allows the composition of various channels, and the multi-channel audio system of this study can be effectively applied at any place where live music is needed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.3
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• pp.13-20
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• 2013

In this paper, we propose a multi-scale crack detection method. This method uses decomposition, composition, and shape properties. It is based on morphology algorithm, crack features. We use a morphology operator which extracts patterns of crack. It segments cracks and background using opening and closing operations. Morphology based segmentation is better than existing integration methods using subtraction in detecting a crack it has small width. However, morphology methods using only one structure element could detect only fixed width crack. Thus, we use decomposition and composition methods. We use a decimation method for decomposition. After decomposition and morphology operation, we get edge images given by binary values. Our method calculates values of properties such as the number of pixels and the maximum length of the segmented region. We decide whether the segmented region belongs to cracks according to those data. Experimental results show that our proposed multi-scale crack detection method has better results than those of existing detection methods.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.887-890
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• 1998

We present a novel multi-resolution block matching algorithm (BMA) for fast motion estimation. At the coarsest level, a full search BMA (FSBMA) is performed for searching complex or random motion. Concurrently, spatial correlation of motion vector (MV) field is used for searching continuous motion. Here we present an efficient method for searching full resolution MVs without MV decimation even at the coarsest leve. After the coarsest level search, two or three initial MV candidates are chosen for the next level. At the further levels, the MV candidates are refined within much smaller search areas. Simulation results show that in comparison with FSBMA, the proposed BMA achieves a speed-up factor over 710 with minor PSNR degradation of 0.2dB at most, under a normal MPEG2 coding environment. Furthermore, our scheme is also suitable for hardware implementation due to regular data-flow.

• Journal of Sensor Science and Technology
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• v.26 no.5
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• pp.348-352
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• 2017

In this paper, we propose a high resolution A/D converter for a sensor interface that processes low frequency AC signals. A 6b SAR ADC with low power consumption and a 11b incremental ADC with high resolution are combined together to perform 15b resolution. Conventional hybrid ADC has a disadvantage that it can convert t only DC signal, but in this paper, it is possible to convert data to AC signal by increasing input range of incremental ADC. The decimation filter is implemented on-chip. The designed Hybrid ADC operates at supply voltage of 1.8V and consumes the current of 6.98uA. The OSR (oversampling ratio) is 90. And SFDR, SNDR, ENOB and FoMs are 96.59dB, 88.47dB, 14.4-bit and 139.5dB, respectively.

• Journal of Biomedical Engineering Research
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• v.12 no.4
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• pp.295-302
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• 1991

In this paper, the inter- and intra-frame distortions in the gray levels of a series of fluorescein ocular fundus photographs are corrected. For doing this, the background images are extracted from original images using the image blurring effect by decimation, and then shading corrected images are obtained by subtracting the background images from the original images pixel by pixel. In a series of fluorescein ocular fundus photographs, after the gray scale distoriton is corrected, the intensity volumes of dye leakage are measured and represented by a graph. These data may be useful for the prediction of prognosis and the therapeutic management.

• Journal of Korea Multimedia Society
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• v.11 no.12
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• pp.1668-1675
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• 2008

In this paper, we propose a post-processing technique developed for the subjective improvement of color resolution in DCT-coded color images. The high frequency components caused by complex object parts are compressed and impaired through DCT-based image processing, so color distortions such as blurs in high saturated regions are observed. It's mainly due to the severe loss of color data as Cb and Cr. Generally, the activities of chroma elements in DCT domain correlate strongly with that of luminance as spatial frequency gets higher, and based on the relations between chroma and luma AC activities, we compensate destructed Cb, Cr coefficients using modifications from Y coefficients. Simulation results show that the proposed method enhances color resolution in high saturated region, and improves the visual quality.