• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.5
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• pp.1238-1259
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• 2024

Previous studies on joint optimization of computation offloading and service caching policies in Mobile Edge Computing (MEC) have often neglected the impact of dependency-aware subtasks, edge server resource constraints, and multiple users on policy formulation. To remedy this deficiency, this paper proposes a many-objective joint optimization dependency-aware task offloading and service caching model (MaJDTOSC). MaJDTOSC considers the impact of dependencies between subtasks on the joint optimization problem of task offloading and service caching in multi-user, resource-constrained MEC scenarios, and takes the task completion time, energy consumption, subtask hit rate, load variability, and storage resource utilization as optimization objectives. Meanwhile, in order to better solve MaJDTOSC, a many-objective evolutionary algorithm TSMSNSGAIII based on a three-stage mating selection strategy is proposed. Simulation results show that TSMSNSGAIII exhibits an excellent and stable performance in solving MaJDTOSC with different number of users setting and can converge faster. Therefore, it is believed that TSMSNSGAIII can provide appropriate sub-task offloading and service caching strategies in multi-user and resource-constrained MEC scenarios, which can greatly improve the system offloading efficiency and enhance the user experience.

• Journal of the Korean Mathematical Society
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• v.54 no.3
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• pp.793-805
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• 2017

In this paper, we prove that the Ricci tensor of a three-dimensional almost Kenmotsu manifold satisfying ${\nabla}_{\xi}h=0$, $h{\neq}0$, is ${\eta}$-parallel if and only if the manifold is locally isometric to either the Riemannian product $\mathbb{H}^2(-4){\times}\mathbb{R}$ or a non-unimodular Lie group equipped with a left invariant non-Kenmotsu almost Kenmotsu structure.

• Electronics and Telecommunications Trends
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• v.9 no.4
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• pp.9-21
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• 1994

Wide variety of the architectural complexity of parallel computer often makes it difficult to develop efficient programs for them. One of approaches to improve this difficulty is to program in familiar sequential languages such as Fortran or C and to parallelize sequential programs into equivalent parallel programs automatically. This paper presents an organization of parallelizing compiler which transforms sequential programs into equivalent parallel programs. The parallelizer consists mainly of syntax analysis, control and data flow analysis, program transformation, and parallel code generation. In particular, the program restructuring in this parallelizer maximizes loop parallelism.

• ETRI Journal
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• v.13 no.2
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• pp.34-41
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• 1991

In this paper, a new distributed parallel algorithm for pattern classification based upon Self-Organizing Neural Network(SONN)[10-12] is developed. This system works without any information about the number of clusters or cluster centers. The SONN model showed good performance for finding classification information, cluster centers, the number of salient clusters and membership information. It took a considerable amount of time in the sequential version if the input data set size is very large. Therefore, design of parallel algorithm is desirous. A new distributed parallel algorithm is developed and experimental results are presented.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.1
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• pp.101-108
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• 2000

The data prefetching scheme is an effective technique to reduce the main memory access latency by exploiting the overlap of processor computations with data accesses. However, if the prefetched data replicate the useful existing data in the cache memory and they are not being used in computations. performances of programs are aggravated. This phenomenon results from the lack of correct predictions for data being used in the future. When parallel programs exploit the data arrays for computations, the grain size is useful information for data prefetching scheme because it implies the range of data using in computations. Based on this information, we suggest a new data prefetching scheme exploited by the grain size of the parallel program. Simulation results show that the suggested prefetching scheme improves the performance of the simulated parallel programs due to the reduction of bus transactions as well as useful prefetching operations.

• ETRI Journal
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• v.32 no.2
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• pp.222-229
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• 2010

A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, we propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix multiplications, we derive a well-organized recursive formula and realize a pseudorandom sequence generator with multiple outputs. Experimental results show that, although the total area of the proposed scheme is 3% to 13% larger than that of the existing scheme, our parallel architecture improves the throughput by 2, 4, and 6 times compared with the existing scheme based on a single output. In addition, we apply our approach to a $2{\times}2$ multiple input/multiple output (MIMO) detector targeting the 3rd Generation Partnership Project Long Term Evolution (3GPP LTE) system. Therefore, the throughput of the MIMO detector is significantly enhanced by parallel processing of data communications.

• Proceedings of the KIEE Conference
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• 1998.07b
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• pp.663-665
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• 1998

The measuring data acquisition methods from local sensor are many kinds of techniques. But, if sampling time is not important and we need data of many sensors it is more resonable to be applied economical system. In this paper, the data acquisition technique is used two RS232C communication signals simultaneously. The one come from computer serial port, and another is signal changed from parallel port. In this case the circuits would be simplification and that communication cable is connected by Parallel instead of Branch connection.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.1
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• pp.21-27
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• 2016

An integrated display software platform for small UAV is developed based on parallel processing technique in this paper. When the small UAV with high-performance camera and avionic modules is employed to various surveillance-related missions, it is important to reduce the operator's workload and increase the monitoring efficiency. For this purpose, it is needed to develop an efficient monitoring software enable to manipulate the image and flight data obtained during flight within the given processing time and display them simultaneously. In this paper, we set up requirements and suggest the architecture for the software platform. The integrated software platform is implemented with parallel processing scheme. Based on AR drone, we verified that the various data are concurrently displayed by the suggest software platform.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.1
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• pp.50-55
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• 2004

We propose an intgrated Gill environment system having only integer fuzzy operations in the consequent part and the defuzzification stage. In this paper, we also propose an integrated Gill environment system with 4 parallel fuzzy processing units to be operated in parallel on the classification of the sensed image data. In this, we solve the problems of taking longer times as the fuzzy real computations of [0, 1] by using the integer pixel conversion algorithm to convert lines of each fuzzy linguistic term to the closest integer pixels. This procedure is performed automatically in the GUI application program. As a Gill environment, PCI transmission, image data pre-processing, integer pixel mapping and fuzzy membership tuning are considered. This system can be operated in parallel manner for MIMO or MISO systems.

• 한국전산유체공학회:학술대회논문집
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• 2005.10a
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• pp.157-162
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• 2005

Parallel implementation and performance assessment of the grid assembly in a structured chimera grid approach is studied. The grid assembly process, involving hole cutting and searching donor, is parallelized on the PC cluster. A message passing programming model based on the MPI library is implemented using the single program multiple data(SPMD) paradigm. The coarse-grained communication is optimized with the minimized memory allocation because that the parallel grid assembly can access the decomposed geometry data in other processors by only message passing in the distributed memory system such as a PC cluster. The grid assembly workload is based on the static load balancing tied to flow solver. A goal of this work is a development of parallelized grid assembly that is suited for handling multiple moving body problems with large grid size.