• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.586-590
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• 2001

In this paper, a novel control scheme compensating source voltage unbalance and harmonic currents for hybrid active power filters is proposed, where no low/high-pass filters are used in compensation voltage composition. The phase angle and compensation voltages for source harmonic current and unbalanced voltage components are derived from the positive sequence component of the unbalanced voltage set, which is simply obtained by using digital all-pass filters. Since a balanced set of the source voltage obtained by scaling the positive sequence components is used as reference values for source current and load voltage, it is possible to eliminate the necessity of low/high-pass filters in the reference generation. Therefore the control algorithm is much simpler and gives more stable performance than the conventional method. In addition, the source harmonic current is eliminated by compensating for the harmonic voltage of the load side added to feedback control of the fundamental component.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.373-376
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• 1999

This paper propose a "common mode voltage damper" that is capable of reducing the common mode voltage produced in the PWM VSI. An push-pull circuits and high frequency leakage current damper[1] are incorporated into the "common mode voltage damper", the design method of which is presented. Effect of "common mode voltage damper" is simulated in this paper verifies the viability and effectiveness in 2.2kW induction motor drive using IGBT inverter. Simulated results show that "common mode voltage damper" makes significant contributions to reducing a high frequency leakage current.ducing a high frequency leakage current.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.343-346
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• 2002

In recent, complex SVPWM (Space Vector PWM) algorithm can be easily implemented by high performance microprocessor and DSP. Various SVPWM techniques are widely studied due to the advantages of low harmonic distortion and high use ratio of D.C. link voltage. Most of various studies for improving of VS-PWM inverter performance are concentrated about switching pattern and zero pulse pattern split algorithms. However, dc link voltage that is determined at rated load and speed conditions is not proper in the low speed and under rated load. In this paper, analysis of current ripple with digitally implemented SVPWM inverter is introduced according to link voltage. The optimal link voltage in the designed inverter system and load condition is provided in order to suppress output voltage error and current ripple. As remaining the effective voltage vector interval per sampling period sufficiently, additional voltage error and current ripple are suppressed. The proposed algorithm is verified through digital simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• 제9권5호
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• pp.1632-1642
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• 2014

This paper presents an interleaved resonant converter to reduce the voltage stress of power MOSFETs and achieve high circuit efficiency. Two half-bridge converters are connected in series at high voltage side to limit MOSFETs at $V_{in}/2$ voltage stress. Flying capacitor is used between two series half-bridge converters to balance two input capacitor voltages in each switching cycle. Variable switching frequency scheme is used to control the output voltage. The resonant circuit is operated at the inductive load. Thus, the input current of the resonant circuit is lagging to the fundamental input voltage. Power MOSFETs can be turn on under zero voltage switching. Two resonant circuits are connected in parallel to reduce the current stress of transformer windings and rectifier diodes at low voltage side. Interleaved pulse-width modulation is adopted to decrease the output ripple current. Finally, experiments are presented to demonstrate the performance of the proposed converter.

• 한국철도학회:학술대회논문집
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• 한국철도학회 1998년도 추계학술대회 논문집
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• pp.171-178
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• 1998

This paper proposes a new overmodulation strategy to give a better voltage utilization by tracking voltage vector along hexagon sides. This strategy enables the inverter to control both magnitude and angle of current. Therefore, the vector control using this strategy can lead to better output torque dynamics compared to the conventional slip frequency control with six-step voltage, which is widely used in the traction drive. In this strategy, the d-axis output voltage of a current controller to control the flux is conserved and the q-axis output voltage to control the torque is controlled to place the voltage vector on the hexagon boundary In case of overmodulation. The limited q-axis voltage is used for anti-windup of q-axis current controller. This paper also presents a new field weakening scheme which incorporate the proposed overmodulation strategy. In this scheme, the flux level is selected by both required current limit and the available maximum voltage along hexagon sides. The validity of the proposed overall scheme is confirmed by the computer simulations for a typical traction drive with a 210[㎾] induction motor.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2022년도 춘계학술대회
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• pp.560-561
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• 2022

본 논문은 Nanosheet FET(NSFET)와 FinFET의 소자 성능을 3차원 소자 시뮬레이션을 통하여 다양한 구조의 NSFET와 FinFET의 소자 시뮬레이션을 한다. NSFET와 FinFET의 전류-전압 특성을 시뮬레이션하였고, 그 전류-전압 특성으로부터 추출한 문턱전압, 문턱전압이하 기울기 등의 성능을 비교하였다. NSFET이 FinFET보다 전류-전압 특성에서 드레인 전류가 더 많이 흐르며 더 높은 문턱전압을 갖는다. 문턱전압이하 기울기는 NSFET와이 FinFET보다 더 가파른 기울기를 갖는다.

• 한국전기전자재료학회논문지
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• 제23권8호
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• pp.593-600
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• 2010

In this paper, High brightness LED (light-emitting diodes) driver IC (integrated circuit) using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET (metal oxide semiconductor field effect transistor) from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. To confirm the functioning and characteristics of our proposed LED driver IC, we designed a buck converter. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses 1.0 ${\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre (Cadence) simulation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.9-9
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• 2010

In this paper, High Brightness LED driver IC using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses $1{\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre(Cadence) simulation.

• 한국정보통신학회논문지
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• 제20권7호
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• pp.1311-1316
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• 2016

본 연구에서는 단채널 비대칭 이중게이트 MOSFET의 채널길이에 따른 문턱전압이동에 터널링전류가 미치는 영향을 분석하고자 한다. 채널길이가 10 nm 이하로 감소하면 터널링 전류는 급격히 증가하여 문턱전압이동 등 2차효과가 발생한다. 단채널 효과를 감소시키기 위하여 개발된 비대칭 이중게이트 MOSFET의 경우에도 터널링 전류에 의한 문턱전압이동은 무시할 수 없게 된다. 차단전류는 열방사전류와 터널링 전류로 구성되어 있으며 채널길이가 작아질수록 터널링전류의 비율은 증가한다. 본 연구에서는 터널링 전류를 분석하기 위하여 WKB(Wentzel-Kramers-Brillouin) 근사를 이용하였으며 채널 내 전위분포를 해석학적으로 유도하였다. 결과적으로 단채널 비대칭 이중게이트 MOSFET에서는 채널길이 가 작아질수록 터널링 전류의 영향에 의한 문턱전압이동이 크게 나타나고 있다는 것을 알 수 있었다. 특히 하단게이트 전압 등에 따라 터널링 전류에 의한 문턱전압 값은 변할지라도 문턱전압이동은 거의 일정하였다.

• 전자공학회논문지C
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• 제34C권9호
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• pp.1-9
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• 1997

Novel class A CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well standard CMOS process for high-frequency current-mode signal processing were developed. The CCII consists of a regulated current-cell for the voltage input and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated cCII show that the current input impedance is 308 .ohm. and the 3-dB cutoff frequency when used as a voltage amplifier extends beyond 10MHz. The linear dynamic ranges of voltage and current are from -0.5V to 1.5V and from -100.mu.A to +120.mu.A for supply voltage V$\_$DD/ = -V$\_$SS/=2.5V, respectively. The power dissipation is 2 mW and the active chip area is 0.2 * 0.2 [mm$\^$2/].