Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지
DOI QR코드

DOI QR Code

Influence of Tunneling Current on Threshold voltage Shift by Channel Length for Asymmetric Double Gate MOSFET

비대칭 DGMOSFET에서 터널링 전류가 채널길이에 따른 문턱전압이동에 미치는 영향

  • Jung, Hakkee (Department of Electronic Engineering, Kunsan National University)
  • Received : 2016.01.22
  • Accepted : 2016.02.17
  • Published : 2016.07.31
Download PDF
⟨ Previous Next ⟩

Abstract

This paper analyzes the influence of tunneling current on threshold voltage shift by channel length of short channel asymmetric double gate(DG) MOSFET. Tunneling current significantly increases by decrease of channel length in the region of 10 nm below, and the secondary effects such as threshold voltage shift occurs. Threshold voltage shift due to tunneling current is not negligible even in case of asymmetric DGMOSFET to develop for reduction of short channel effects. Off current consists of thermionic and tunneling current, and the ratio of tunneling current is increasing with reduction of channel length. The WKB(Wentzel-Kramers-Brillouin) approximation is used to obtain tunneling current, and potential distribution in channel is hermeneutically derived. As a result, threshold voltage shift due to tunneling current is greatly occurred for decreasing of channel length in short channel asymmetric DGMOSFET. Threshold voltage is changing according to bottom gate voltages, but threshold voltage shifts is nearly constant.

본 연구에서는 단채널 비대칭 이중게이트 MOSFET의 채널길이에 따른 문턱전압이동에 터널링전류가 미치는 영향을 분석하고자 한다. 채널길이가 10 nm 이하로 감소하면 터널링 전류는 급격히 증가하여 문턱전압이동 등 2차효과가 발생한다. 단채널 효과를 감소시키기 위하여 개발된 비대칭 이중게이트 MOSFET의 경우에도 터널링 전류에 의한 문턱전압이동은 무시할 수 없게 된다. 차단전류는 열방사전류와 터널링 전류로 구성되어 있으며 채널길이가 작아질수록 터널링전류의 비율은 증가한다. 본 연구에서는 터널링 전류를 분석하기 위하여 WKB(Wentzel-Kramers-Brillouin) 근사를 이용하였으며 채널 내 전위분포를 해석학적으로 유도하였다. 결과적으로 단채널 비대칭 이중게이트 MOSFET에서는 채널길이 가 작아질수록 터널링 전류의 영향에 의한 문턱전압이동이 크게 나타나고 있다는 것을 알 수 있었다. 특히 하단게이트 전압 등에 따라 터널링 전류에 의한 문턱전압 값은 변할지라도 문턱전압이동은 거의 일정하였다.

Keywords

References

  1. Bodnara, 10 nm FinFET added to Samsung Foundry's Process Roadmap [internet]. http://www.bodnara.co.kr/bbs/article.html?num=124108.
  2. W.S.Cho and K.Roy, "The Effects of Direct Source-to-Drain Tunneling and Variation in the Body Thickness on (100) and (110) Sub-10-nm Si Double-Gate Transistors," IEEE Electron Device Letters, vol. 36, no. 5, pp. 427-429, May 2015. https://doi.org/10.1109/LED.2015.2413785
  3. N. Bagga and S.K. Sarkar, "An Analytical Model for Tunnel Barrier Modulation in Triple Metal Double Gate TFET," IEEE Trans. Electron Devices, vol. 62, no. 7, pp. 2136-2142, July 2015. https://doi.org/10.1109/TED.2015.2434276
  4. Z.Ding, G.Hu, J.Gu, R.Liu, L.Wang and T.Tang, "An analytical model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs," Microelectronics J., vol. 42, pp. 515-519, March 2011. https://doi.org/10.1016/j.mejo.2010.11.002
  5. L.D.Landau and E.M.Lifshitz, Quantum Mechanics, Addison-Wesley, Reading Mass., p.174, 1958.
  6. D.S.Havaldar, G.Katti, N.DasGupta and A.DasGupta, "Subthreshold Current Model of FinFETs Based on Analytical Solution of 3-D Poisson's Equation," IEEE Trans. on Electron Devices, vol. 53, no. 4, pp. 737-741, April 2006. https://doi.org/10.1109/TED.2006.870874
  7. H.K.Jung, "Analysis for Potential Distribution of Asymmetric Double Gate MOSFET Using Series Function," J. of KIICE, vol. 17, no. 11, pp. 2621-2626, Nov. 2013.
  8. Q.Chen, B.Agrawal and J.D.Meindl, "A Comprehensive Analytical Subthreshold Swing(S) Model for Double-Gate MOSFETs," IEEE Trans. Electron Devices, vol. 49, no.6, pp.1086-1090, June 2002. https://doi.org/10.1109/TED.2002.1003757
  9. M.Stadele, "Influence of source-drain tunneling on the subthreshold behavior of sub-10 nm double gate MOSFETs," in Proc. Eur. Solid-State Device Research Conf.(ESSDERC), Florence, Italy, pp. 135-138, 2002.
  10. H.K.Jung and O.S.Kwon, "Analysis of Channel Dimension Dependent Threshold Voltage for Asymmetric DGMOSFET," 2014 International Conference on Future Information & Communication Engineering, Hong Kong:HK, vol. 6, no. 1, pp. 299-302, 2014.

Cited by

  1. 10 nm 이하 DGMOSFET의 항복전압과 채널도핑농도의 관계 vol.21, pp.6, 2016, https://doi.org/10.6109/jkiice.2017.21.6.1069
  2. 10 nm 이하 저도핑 DGMOSFET의 SPICE용 DIBL 모델 vol.21, pp.8, 2017, https://doi.org/10.6109/jkiice.2017.21.8.1465