• 한국태양에너지학회:학술대회논문집
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• 2011.11a
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• pp.245-248
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• 2011

Many researches have been carried out to improve light absorption in the crystalline silicon solar cell fabrication. The rear reflection is applied to increase the path length of light, resulting in the light absorption enhancement and thus the efficiency improvement mainly due to increase in short circuit current. In this paper, we manufactured the silicon solar cell using the mono crystalline silicon wafers with $156{\times}156mm^2$, 0.5~3.0 ${\Omega}{\cdot}cm$ of resistivity and p-type. After saw damage removal, the dielectric film ($SiN_x$)on the back surface was deposited, followed by surface texturing in the KOH solution. It resulted in single-side texturing wafer. Then the dielectric film was removed in the HF solution. The silicon wafers were doped with phosphorus by $POCl_3$ with the sheet resistance 50 ${\Omega}/{\Box}$ and then the silicon nitride was deposited on the front surface by the PECVD with 80nm thickness. The electrodes were formed by screen-printing with Ag and Al paste for front and back surface, respectively. The reflectance and transmittance for the single-sided and double-sided textured wafers were compared. The double-sided textured wafer showed higher reflectance and lower transmittance at the long wavelength region, compared to single-sided. The completed crystalline silicon solar cells with different back surface texture showed the conversion efficiency of 17.4% for the single sided and 17.3% for the double sided. The efficiency improvement with single-sided textured solar cell resulted from reflectance increase on back surface and light absorption enhancement.

• Journal of the Semiconductor & Display Technology
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• v.12 no.3
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• pp.41-46
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• 2013

Efficient and inexpensive solar cells are necessary for photo-voltaic to be widely adopted for mainstream electricity generation. For this to occur, the recombination losses of charge carriers (i.e. electrons or holes) must be minimized using a surface passivation technique suitable for manufacturing. Recently it has been shown that aluminum oxide thin films are negatively charged dielectrics that provide excellent surface passivation of silicon solar cells to attract positive-charged holes. Especially aluminum oxide thin film is a quite suitable passivation on the rear side of p-type silicon solar cells. This paper, it demonstrate the interfacial microstructure and electrical properties of mono-crystalline silicon surface passivated by $Al_2O_3$ films during firing process as applied for screen-printed solar cells. The first task is a comparison of the interfacial microstructure and chemical bonds of PECVD $Al_2O_3$ and of PEALD $Al_2O_3$ films for the surface passivation of silicon. The second is to study electrical properties of double-stacked layers of PEALD $Al_2O_3$/PECVD SiN films after firing process in the temperature range of $650{\sim}950^{\circ}C$.

• Korean Journal of Materials Research
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• v.27 no.8
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• pp.403-408
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• 2017

We investigated the effect of ZnO buffer layer on the formation of ZnO thin film by ultrasonic assisted spray pyrolysis deposition. ZnO buffer layer was formed by wet solution method, which was repeated several times. Structural and optical properties of the ZnO thin films deposited on the ZnO buffer layers with various cycles and at various temperatures were investigated by field-emission scanning electron microscopy, X-ray diffraction, and photoluminescence spectrum analysis. The structural investigations showed that three-dimensional island shaped ZnO was formed on the bare Si substrate without buffer layers, while two-dimensional ZnO thin film was deposited on the ZnO buffer layers. In addition, structural and optical investigations showed that the crystalline quality of ZnO thin film was improved by introducing the buffer layers. This improvement was attributed to the modulation of the surface energy of the Si surface by the ZnO buffer layer, which finally resulted in a modification of the growth mode from three to two-dimensional.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.315-315
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• 2016

The hydrogenated amorphous silicon (a-Si:H) thin film solar cells using n/Al or n/Ag/Al back reflector have low short circuit current (Jsc) due to high absorption coefficients of Al or work function difference between n-layer and the metal. In this article, we utilized aluminum doped zinc oxide (AZO) to raise the internal reflectance for the improvement of short current density (Jsc) in a-Si:H thin film solar cells. It was found that there was a slight increase in the reflectance in the long wavelength range at the process temperature of 125oC due to improved crystalline quality of the AZO back reflector. The optical band gap (Eg) and work function were affected by the temperature and so did the internal reflectance. The increased internal reflectance within the solar cell resulted in Jsc of 14.94 mA/cm2 and the efficiency of 8.84%. Jsc for the cell without back reflector was 12.29 mA/cm2.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.11
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• pp.922-925
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• 2012

Single crystalline Au nanowires were successfully synthesized in a tube-type furnace. The Au nanowires were grown by vapor phase synthesis technique using solid-liquid-solid (SLS) mechanism on substrates of corning glass and Si wafer. Prior to Au nanowire synthesis, Au thin film served as both catalyst and source for Au nanowire was prepared by sputtering process. Average length of the grown Au nanowires was approximately 1 ${\mu}m$ on both the corning glass and Si wafer substrates, while the diameter and the density of which were dependent on the thickness of the Au thin film. To induce a super-saturated states for the Au particle catalyst and Au molecules during the Au nanowire synthesis, thickness of the Au catalyst thin film was fixed to 10 nm or 20 nm. Additionally, synthesis of the Au nanowires was carried out without introducing carrier gas in the tube furnace, and synthesis temperature was varied to investigate the temperature effect on the resulting Au nanowire characteristics.

• Proceedings of the KIEE Conference
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• 1989.07a
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• pp.662-666
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• 1989

Pure mono Silane(Purity: 99.99%) was used as a thin film source and [$SiH_4$ + $H_2$ (5%)] + [$PH_3$ + $H_2$(0.05%)] mixed dilute gas was used for p-n junction diode. The substrate was P-type silicon wafer (p=$3{\Omega}$ cm) with the direction (100). The crystalline qualities of deposited thin film were investigated by the X-ray diffraction, RHEED and TED patterns and the voltampere characteristics of p-n junction diode was identified by I-V curve.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.2
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• pp.147-152
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• 2002

Carbon nitride thin films were deposited by reactive sputtering for the hard coating materials on Si wafer and tool steels. When the nitrogen content of carbon nitride film on tool steel is 33.4%, the mean hardness and elastic modulus are 49.34 GPa and 307.2 GPa respectively. The nitrided or carburised surface acts as the diffusion barrier which shows better adhesion of carbon nitride thin film on the steel surface. To prevent nitrogen diffusion from the film, steel substrate can be saturated by nitrogen forming a Fe$_3$N layer. The desirable structure at the surface after carburising is martensite, but sometimes, due to high carbon content an proeutectoid Fe$_3$C structure may form at the grain boundaries, leaving the overall surface brittle and may cause defects.

• Journal of the Korean institute of surface engineering
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• v.32 no.3
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• pp.235-238
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• 1999

Silicon dioxide films were prepared by anodizing silicon wafers in an ethylene $glycol+HNO_3(0.04{\;}N)$ at 20 to $70^{\circ}C$. The voltage between silicon anode and platinum cathode was measured during this process. Under the constant current electrolysis, the voltage increased with oxide film growth. The transition time at which the voltage reached the predetermined value depended on the temperature of the electrolyte. After the time of electrolysis reached the transition time, the anodization was changed the constant voltage mode. The depth profile of oxide film/Si substrate was confirmed by XPS analysis to study the influence of the electrolyte temperature on the anodization. Usually, the oxide-silicon peaks disappear in the silicon substrate, however, this peak was not small at $45^{\circ}C$ in this region.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1598-1600
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• 2003

Microcrystalline silicon(c-Si:H) thin-film solar cells are prepared with intrinsic Si-layer by hot wire CVD. The operating parameters of solar cells are strongly affected by the filament temperature ($T_f$) during intrinsic layer. Jsc and efficiency abruptly decreases with elevated $T_f$ to $1400^{\circ}C$. This deterioration of solar cell parameters are resulted from increase of crystalline volume fraction and corresponding defect density at high $T_f$ The heater temperature ($T_h$) are also critical parameter that controls device operations. Solar cells prepared at low $T_h$ (<$200^{\circ}C$) shows a similar operating properties with devices prepared at high $T_f$, i.e. low Jsc, Voc and efficiency. The origins for this result, however, are different with that of inferior device performances at high $T_f$. In addition the phase transition of the silicon films occurs at different silane concentration (SC) by varying filament temperature, by which highest efficiency with SC vanes with $T_f$.

• Electrical & Electronic Materials
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• v.16 no.9
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• pp.64.1-64
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• 2003

A metal-ferroelectric [SrBi$_2$Ta$_2$O$\_$9/ (SBT)-high-k-insulator(PrOx)-semiconductor(Si) structure has been fabricated and evaluated as a key part of metal-ferroelectric-insulator-semiconductor-field-effect-transistor MFIS-FET memory, aiming to improve the memory retention characteristics by increasing the dielectric constant in the insulator layer and suppressing the depolarization field in the SBT layer. A 20-nm PrOx film grown on Si(100) showed both a high of about 12 and a low leakage current density of less than 1${\times}$ 10e-8 A/$\textrm{cm}^2$ at 105 MV/cm. A 400-nm SBT film prepared on PrOx/Si shows a preferentially oriented (105) crystalline structure, grain size of about 130 nm and subface roughness of 3.2 nm. A capacitance-voltage hysteresis is confirmed on the Pt/SBT/PrOx/Si diode with a memory window of 0.3V at a sweep voltage width of 12 V. The memory retention time was about 1 104s, comparable to the conventional Pt/SBT/SiO$\_$x/N$\_$y/(SiO$\_$N/)/Si. The gradual change of the capacitance indicates that some memory degradation mechanism is different from that in the Pt/SBT/SiON/Si structure.