• Journal of Communications and Networks
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• 제15권6호
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• pp.614-634
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• 2013

The proliferation of real-time multimedia services requires huge amounts of data transactions demanding strict quality-of-service (QoS) guarantees. Multicast transmission is a promising technique because of its efficient network resource utilization. However, high head-of-line (HOL) blocking probability and lack of service-specific QoS control should be addressed for practical implementations of multicast networks. In this paper, a topology aware fanout set division (TAFD) scheme is proposed to resolve these problems. The proposed scheme is composed of two techniques that reduce HOL blocking probability and expedite packet delivery for large-delay branches regarding multicast tree topology. Since management of global topology information is not necessary, scalability of the proposed scheme is guaranteed. Mathematical analysis investigates effects of the proposed scheme and derives optimal operational parameters. The evaluation results show that the TAFD scheme achieves significant delay reduction and satisfies required delay bounds on various multicast networks.

• Journal of the Microelectronics and Packaging Society
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• 제26권1호
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• pp.1-7
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• 2019

Recently, memristor (anion-based memristor) is referred to as the fourth circuit element which resistance state can be gradually changed by the electric pulse signals that have been applied to it. And the stored information in a memristor is non-volatile and also the resistance of a memristor can vary, through intermediate states, between high and low resistance states, by tuning the voltage and current. Therefore the memristor can be applied for analogue memory and/or learning device. Usually, memristive behavior is easily observed in the most transition metal oxide system, and it is explained by electrochemical migration motion of anion with electric field, electron scattering and joule heating. This paper reports the latest trends and issues of anion-based memristor.

• Journal of the Korean Institute of Telematics and Electronics B
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• 제29B권4호
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• pp.1-11
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• 1992

A parallel computer "KAPAC(KAIST Parallel Computer)" based on Transputer is designed and implemented. Its purpose is to support the real time processing and high perfomance computing through parallelizing the complex and heavy computation load. KAPAC has UNIX machine as host-computer and is implemented on VME bus as back-end machine. The parallel computer "KAPAC" is the message-passing loosely-coupled multiprocessor computer having thirty two processing elements, and the network topology between processing elements can be easily configured with the crossbar switchs using the control program. Various topologies are introduced and appoication programs are executed on the parallel computer "KAPAC" with eifferent interconnection topologies to show the reconfigurability.to show the reconfigurability.

• International Journal of Internet, Broadcasting and Communication
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• 제12권3호
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• pp.9-17
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• 2020

In this paper, as part of the research for the infrastructure of very high flexible and reconfigurable data center using very high speed crossbar switches, we developed a simulator that can model two and three dimensional connection structure of switches with an efficient control algorithm using software defined network and verified the functions and analyzed the performance accordingly. The simulator consists of a control module and a switch module that was coded using Python language based on the Mininet and Ryu Openflow frameworks. The control module dynamically controls the operation of switching cells using a shortest multipath algorithm to calculate efficient paths adaptively between configurable computing resources. Performance analysis by using the simulator shows that the three-dimensional switch architecture can accommodate more hosts per port and has about 1.5 times more successful 1:n connections per port with the same number of switches than the two-dimensional architecture. Also simulation results show that connection length in a 3-dimensional way is shorter than that of 2-dimensional way and the unused switch ratio in a 3-dimensional case is lower than that of 2-dimensional cases.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제24권11호
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• pp.855-858
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• 2011

In this paper, in order to suppress unwanted current paths originating from adjacent cells in a passive crossbar array based on resistive random access memory (RRAM) without extrinsic switching devices, 1-diode type RRAM which consists of a 0.2% chromium-doped strontium titanate (Cr-$SrTiO_3$) film deposited on a silicon substrate, was proposed for high packing density, and intrinsic rectifying characteristics from the current versus voltage characteristics were successfully demonstrated.

• Proceedings of the KIEE Conference
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• 대한전기학회 1990년도 하계학술대회 논문집
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• pp.532-534
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• 1990

We suggest a new energy function that improves the area complexity of the Hopfield Crossbar Network. Through converting data representation to an encoded format, we reduce the number of nodes of the network, and thus reduce the entire size. We apply this approach to the layer assignment problem, and use the modified delayed self-feedback Hopfield Network. Area complexity of the existing network for layer assignment ploblem is improved from O( $N^2L^2$ ) to O($N^2$(log L)$^2$).

• Proceedings of the IEEK Conference
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.991-992
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• 2006

Multiprocessor system is efficient and high performance architecture to overcome a limitation of single core SoC. In this paper, we propose a multiprocessor SoC (MPSoC) architecture which provides the low complexity and the high performance. The dynamic routing scheme has a serious problem in which the complexity of routing increases exponentially. We solve this problem by making a cluster with several PEs (Processing Element). In inter-cluster network, we use deterministic routing scheme and in intra-cluster network, we use dynamic routing scheme. In order to control the hierarchical network, we propose efficient router architecture by using smart crossbar switch. We modeled 2-D mesh topology and used simulator based on C/C++. The results of this routing scheme show that our approach has less complexity and improved throughput as compared with the pure deterministic routing architecture and the pure dynamic routing architecture.

• The Journal of the Korea institute of electronic communication sciences
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• 제10권10호
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• pp.1123-1130
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• 2015

Network on a chip(NoC) is a communication subsystem between intellectual property(IP) cores in a SoC and improves high performance in the scalability and the power efficiency compared with conventional buses and crossbar switches. NoC needs a synchronizer to overcome the metastability problem between data links. This paper presents a new mesochronous synchronizer(MS) which is composed of selection window generator, selection signal generator, and data buffer. A delay line circuit is used to build selection window in selection window generator based on the delayed clock cycle of transmitted clock and the transmitted clock is compared with local clock to generate a selection signal in the SW(selection window). This MS gets rid of the restriction of metastability by choosing a rising edge or a falling edge of local clock according to the value of selection signal. The simulation results show that the proposed MS operates correctly for all phase differences between a transmitted clock and a local clock.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.48-59
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• 2015

In recent years, there are increasing threats of rootkits that undermine the integrity of a system by manipulating OS kernel. To cope with the rootkits, in Vigilare, the snoop-based monitoring which snoops the memory traffics of the host system was proposed. Although the previous work shows its detection capability and negligible performance loss, the problem is that the proposed design is not acceptable in recent commodity mobile application processors (APs) which have become de facto the standard computing platforms of smart devices. To mend this problem and adopt the idea of snoop-based monitoring in commercial products, in this paper, we propose a snoop-based monitor design called S-Mon, which is designed for the AP platforms. In designing S-Mon, we especially consider two design constraints in the APs which were not addressed in Vigilare; the unified memory model and the crossbar switch interconnect. Taking into account those, we derive a more realistic architecture for the snoop-based monitoring and a new hardware module, called the region controller, is also proposed. In our experiments on a simulation framework modeling a productionquality device, it is shown that our S-Mon can detect the rootkit attacks while the runtime overhead is also negligible.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제46권11호
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• pp.56-65
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• 2009

As increasing the number of IPs integrated in a single chip and requiring high communication bandwidth on a chip, the trend of SoC communication architecture is changed from bus- or crossbar-based architecture to packet switched network architecture, NoC. However, highly complex control logics in routers require multiple cycles to switch packet. In this paper, we design low complex router to improve the communication latency. Our NoC design is verified by simulation platform modeled by ESL tool, SoC Designer. We also evaluate our NoC design comparing to the previous NoC architecture based on VC router. Our results show that our NoC architecture has less communication latency, even small throughput degradation (about 1-2%).