• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.33-44
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• 2011

In this paper, we presents a hybrid on-chip bus architecture based on the AMBA 3.0 AXI protocol for MPSoC with high performance and low power. Among AXI channels, data channels with a lot of traffic are designed by crossbar-switch architecture for massively parallel processing. On the other hand, addressing and write-response channels having a few of traffic is handled by shared-bus architecture due to the overheads of (areas, interconnection wires and power consumption) reduction. In experiments, the comparisons are carried out in terms of time, space and power domains for the verification of proposed hybrid on-chip bus architecture. For $16{\times}16$ bus configuration, the hybrid on-chip bus architecture has almost similar performance in time domain with respect to crossbar on-chip bus architecture, as the masters's latency is differenced about 9% and the total execution time is only about 4%. Furthermore, the hybrid on-chip bus architecture is very effective on the overhead reduction, such as it reduced about 47% of areas, and about 52% of interconnection wires, as well as about 66% of dynamic power consumption. Thus, the presented hybrid on-chip bus architecture is shown to be very effective for the MPSoC interconnection design aiming at high performance and low power.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.8
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• pp.61-67
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• 2010

A characterization procedure for analyzing symmetric coupled MIS(Metal-Insulator-Semiconductor) transmission line is used the same procedure as a general single layer symmetric coupled line with perfect dielectric substrate from the extraction of the characteristic impedance and propagation constant for even- and odd-mode. In this paper, an analysis for a new substrate shielding symmetric coupled MIS structure consisting of grounded crossbar at the interface between Si and SiO2 layer using the Finite-Difference Time-Domain (FDTD) method is presented. In order to reduce the substrate effects on the transmission line characteristics, a shielding structure consisting of grounded crossbar lines over time-domain signal has been examined. Symmetric coupled MIS transmission line parameters for even- and odd-mode are investigated as the functions of frequency, and the extracted distributed frequency-dependent transmission line parameters and corresponding equivalent circuit parameters as well as quality factor for the new MIS crossbar embedded structure are also presented. It is shown that the quality factor of the symmetric coupled transmission line can be improved without significant change in the characteristic impedance and effective dielectric constant.

• Journal of KIISE:Information Networking
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• v.34 no.3
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• pp.193-202
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• 2007

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches under Hot-spot environment is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch. The performance of the multiple-buffered $a{\times}a$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.12
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• pp.35-41
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• 2011

In this paper, an analysis for a new substrate shielding symmetric coupled MIS structure consisting of grounded crossbar at the interface between Si and SiO2 layer using the Finite-Difference Time-Domain(FDTD) method is presented. In order to reduce the substrate effects on the transmission line characteristics, a shielding structure consisting of grounded crossbar lines over time-domain signal has been examined. Parameters of symmetric coupled MIS transmission line with various gaps between crossbars for even- and odd-mode are investigated as the functions of frequency, and the extracted distributed frequency-dependent transmission line parameters and corresponding equivalent circuit parameters as well as quality factor for the new MIS crossbar embedded structure are also presented. It is shown that the quality factor of the symmetric coupled transmission line can be improved without significant change in the characteristic impedance and effective dielectric constant.

• Journal of KIISE:Information Networking
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• v.32 no.2
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• pp.244-253
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• 2005

In this paper, a performance evaluation model of the switch router with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the crossbar switch. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. The performance of the multiple-buffered crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a network that uses the multiple buffered crossbar switches. Less than $2\%$ differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• ETRI Journal
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• v.30 no.1
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• pp.141-151
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• 2008

In this paper, we introduce a new verification platform with ARM- and DSP-based multiprocessor architecture. Its simple communication interface with a crossbar switch architecture is suitable for a heterogeneous multiprocessor platform. The platform is used to verify the function and performance of a DVB-T baseband receiver using hardware and software partitioning techniques with a seamless hardware/software co-verification tool. We present a dual-processor platform with an ARM926 and a Teak DSP, but it cannot satisfy the standard specification of EN 300 744 of DVB-T ETSI. Therefore, we propose a new multiprocessor strategy with an ARM926 and three Teak DSPs synchronized at 166 MHz to satisfy the required specification of DVB-T.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.374-377
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• 2003

In this paper, a performance evaluation model of the Fat-Tree network with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem in the switch network The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on the various sizes of Fat-tree networks that use the multiple a$\times$b buffered crossbar switches. It is observed that both analysis and simulation results are match closely.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.539-541
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• 1990

A new neural network model, based on the Hopfield's crossbar associative network, is presented and shown to be an effective tool for the NP-Complete problems. This model is applied to a class of layer assignment problems for VLSI routing. The results indicate that this modified Hopfield model improves stability and accuracy.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.244-246
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• 1999

본 논문에서는, multiple-buffered crossbar 스위치를 이용한 다층 연결 망의 성능 분석 모형을 제안하고, 스위치에 장착된 buffer의 개수 증가에 따른 성능 향상 추이를 분석하였다. Buffered 스위치 기법은 다층 연결 망 (Multistage Interconnection Network, MIN)의 내부의 데이터 충돌 문제를 효과적으로 해결할 수 있는 방법으로 알려져 있다. 제안된 성능 분석 모형은 먼저 네트웍 내부 임의 스위치 입력 단에 유입되는 데이터 패킷이 buffered 스위치 내부에서 전송되는 패턴을 확률적으로 분석하여 수립하였다. 분석 모형의 수학적 복잡도 절감을 위하여 확률식 유도 과정에 정상상태 확률 rosa(steady state probability)을 도입하였다. 제안한 모형은 스위치의 크기 및 스위치에 장착된 buffer의 수와 무관하게 확대 적용이 가능하다. 제안한 수학적 성능 분석 연구의 실효성 검증을 위하여 병행된 시뮬레이션 처리 결과는 상호 미세한 오차 범위 내에서 모형의 예측 데이터와 일치하는 결과를 보여 분석 모형의 타당성을 입증하였다. 2$\times$2 스위치로 구성된 8$\times$8 MIN을 대상으로 분석을 시행한 결과 스위치에 2~4개의 buffer를 장착했을 경우 unbuffer 스위치 경우와 비교하여 네트웍 정상상태 Throughout의 증가율이 높고 네트웍 Delay 또한 낮아져 효율적인 것으로 나타났다. 따라서 2~2 crossbar 스위치로 구성된 MIN의 경우 스위치에 장착된 buffer의 개수가 네 개 정도일 경우가 가격 대 성능비 면에서 가장 유리한 것으로 연구되었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.684-690
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• 2010

Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.