• Computational Structural Engineering
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• v.9 no.3
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• pp.199-207
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• 1996

When an initially straight thin cylinder is bent, there is a tendency for the cross section to flatten. This phenomenon was investigated by L.G. Brazier in 1927 and is called "Brazier Effect" or "Brazier Theory". The main characteristic is the reduction of carrying capacity due to the decrease of bending stiffness by shortening of thickness with the increase of external load. And the relationship of curvature-bending moment becomes a soft spring type as shown in Fig.2. In this paper, the Brazier theory on plate type structures is investigated from the following view points : (1) What is the Brazier effect? (2) the reason of the occurrence of the Brazier effect in plate type structures by using beam model and (3) factors which cause the brazier effect.

• Korean Journal of Materials Research
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• v.24 no.2
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• pp.87-92
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• 2014

The Notched Ring Test(NRT) has proven to be very useful in determining the slow crack growth behavior of polyethylene pressure pipes. In particular, the test is simple and an order of magnitude shorter in experimental times as compared to the currently used Notched Pipe Test(NPT), which makes this method attractive for use as the accelerated slow crack growth test. In addition, since the NRT specimen is taken directly from the pipe, having maintained the cross-section, processing induced artifacts that would affect the slow crack growth behavior are not altered. This makes the direct comparison to the slow crack growth specimen in pipe from more meaningful. In this study, for comparison with other available slow crack growth methods, including the NPT, the stress intensity factor equation for NRT specimen was developed and demonstrated of its accuracy within 3% of that obtained from the finite element analysis. The equation was derived using a flexure formula of curved beam bending along with numerically determined geometric factors. The accuracy of the equation was successfully tested on 63, 110, 140, 160, 250, and 400 mm nominal pipe diameters, with crack depth ranging from 15 % to 45 % of the pipe wall thickness, and for standard dimensional ratio(SDR) of 9, 11, and 13.6. Using this equation the slow crack results from 110SDR11 NRT specimen were compared to that from the NPT specimen, which demonstrated that the NRT specimen was equivalent to the NPT specimen in creating the slow crack, however in much shorter experimental times.

• Korean Journal of Materials Research
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• v.17 no.2
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• pp.73-80
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• 2007

For the sub-65 nm CMOS process, it is necessary to develop a new silicide material and an accompanying process that allows the silicide to maintain a low sheet resistance and to have an enhanced thermal stability, thus providing for a wider process window. In this study, we have evaluated the property and unit process compatibility of newly proposed composite silicides. We fabricated composite silicide layers on single crystal silicon from $10nm-Ni_{1-x}Co_x/single-crystalline-Si(100),\;10nm-Ni_{1-x}Co_x/poly-crystalline-\;Si(100)$ wafers (x=0.2, 0.5, and 0.8) with the purpose of mimicking the silicides on source and drain actives and gates. Both the film structures were prepared by thermal evaporation and silicidized by rapid thermal annealing (RTA) from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, surface composition, were investigated using a four-point probe, a field emission scanning probe microscope, a field ion beam, an X-ray diffractometer, and an Auger electron depth profi1ing spectroscopy, respectively. Finally, our newly proposed composite silicides had a stable resistance up to $1100^{\circ}C$ and maintained it below $20{\Omega}/Sg$., while the conventional NiSi was limited to $700^{\circ}C$. All our results imply that the composite silicide made from NiCo alloy films may be a possible candidate for 65 nm-CMOS devices.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.57-64
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• 2005

This paper presents a built-in current sensor(BICS) that detects defects in CMOS integrated circuits using the current testing technique. This circuit employs a cross-coupled connected PMOS transistors, it is used as a current comparator. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT) and high speed detection time. In addition, in the operation of the normal mode, the BlCS does not have dissipation of extra power, and it can be applied to the deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The area overhead of a BlCS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS standard technology.

• Computational Structural Engineering
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• v.10 no.4
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• pp.315-325
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• 1997

This paper describes the application of discretized continuum-type optimality criteria (DCOC) and the development of optimum design program for the multispan partially prestressed concrete beams. The cost of construction as objective function which includes the costs of concrete, prestressing steel, non-prestressing steel and formwork is minimized. The design constraints include limits on the maximum deflection, flexural and shear strengths, in addition to ductility requirements, and upper and lower bounds on design variables as stipulated by the design Code. Based on Kuhn-Tucker necessary conditions, the optimality criteria are explicitly derived in terms of the design variables-effective depth, eccentricity of prestressing steel and non-prestressing steel ratio. The prestressing profile is prescribed by parabolic functions. The self-weight of the structure is included in the equilibrium equation of the real system, as is the secondary effect resulting from the prestressing force. An iterative procedure and computer program for updating the design variables are developed. Two numerical examples of multispan PPC beams with rectangular cross-section are solved to show the applicability and efficiency of the DCOC-based technique.

• Korean Journal of Optics and Photonics
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• v.18 no.2
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• pp.162-166
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• 2007

In this paper, we propose a WDM optical true time-delay (OTTD) beam former for phased way antenna (PAA) systems. It is composed of a delay lines matrix and a multiwavelength source with discrete DFB laser diodes. The building block of a delay lines matrix is a $2\times2$ optical MEMS switch with proper fiber-optic delay line connected between cross ports. A $4\times3$ matrix using four DFB lasers has been fabricated with unit time-delay difference of 12 ps. Maximum time-delay error was measured to be -1.74 ps and +1.14 ps at a radiation angle of $46.05^{\circ}$, corresponding to error range of $-2.87^{\circ}\sim+1.88^{\circ}$. By measuring time-delays at six different RF frequencies from 5- to 10-GHz, we verified the true time-delay characteristic of our OTTD.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.7
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• pp.81-88
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• 2004

In case of mechanical down tilting, a horizontal pattern is distorted and beam width widens whenincreasing tilt angle, which causes an expansion of hand off region and burden base station equipment. In contrast, electrical down tilting has advantage that horizontal HPBW is kept constant with down tilting. In this paper, based on a phased array technology, dual polarized base station antenna with electrical down tilting was developed at 800MHz band. The antenna has down tilting range of 0$^{\circ}$ to 14$^{\circ}$, and 15㏈i gain. We use stacked microstrip patch as a radiated element and apply balanced feed technique to improve isolation between ports and discrimination of cross polarization. The effect of electrical down tilting was verified by field test.

• International Journal of Naval Architecture and Ocean Engineering
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• v.5 no.1
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• pp.161-177
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• 2013

High-speed vessels require good resistance and seakeeping performance for safe operations in rough seas. The resistance and seakeeping performance of high-speed vessels varies significantly depending on their hull forms. In this study, three planing hulls that have almost the same displacement and principal dimension are designed and the hydrodynamic characteristics of those hulls are estimated by high-speed model tests. All model ships are deep-V type planing hulls. The bows of no.2 and no.3 model ships are designed to be advantageous for wave-piercing in rough water. No.2 and no.3 model ships have concave and straight forebody cross-sections, respectively. And length-to-beam ratios of no.2 and no.3 models are larger than that of no.1 model. In calm water tests, running attitude and resistance of model ships are measured at various speeds. And motion tests in regular waves are performed to measure the heave and pitch motion responses of the model ships. The required power of no.1 (VPS) model is smallest, but its vertical motion amplitudes in waves are the largest. No.2 (VWC) model shows the smallest motion amplitudes in waves, but needs the greatest power at high speed. The resistance and seakeeping performance of no.3 (VWS) model ship are the middle of three model ships, respectively. And in regular waves, no.1 model ship experiences 'fly over' phenomena around its resonant frequency. Vertical accelerations at specific locations such as F.P., center of gravity of model ships are measured at their resonant frequency. It is necessary to measure accelerations by accelerometers or other devices in model tests for the accurate prediction of vertical accelerations in real ships.

• Journal of electromagnetic engineering and science
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• v.18 no.2
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• pp.117-128
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• 2018

In this paper, compact linear dual polarized series-fed $1{\times}2$ linear and $2{\times}2$ planar arrays antennas for airborne SAR applications are proposed. The proposed antenna design consists of a square radiating patch that is placed on top of the substrate, a quarter wave transformer and $50-{\Omega}$ matched transformer. Matching between a radiating patch and the $50-{\Omega}$ microstrip line is accomplished through a direct coupled-feed technique with the help of an impedance inverter (${\lambda}/4$ impedance transformer) placed at both horizontal and vertical planes, in the case of the $2{\times}2$ planar array. The overall size for the prototype-1 and prototype-2 fabricated antennas are $1.9305{\times}0.9652{\times}0.05106{{\lambda}_0}^3$ and $1.9305{\times}1.9305{\times}0.05106{{\lambda}_0}^3$, respectively. The fabricated structure has been tested, and the experimental results are similar to the simulated ones. The CST MWS simulated and vector network analyzer measured reflection coefficient ($S_{11}$) results were compared, and they indicate that the proposed antenna prototype-1 yields the impedance bandwidth >140 MHz (9.56-9.72 GHz) defined by $S_{11}$<-10 dB with 1.43%, and $S_{21}$<-25 dB in the case of prototype-2 (9.58-9.74 GHz, $S_{11}$< -10 dB) >140 MHz for all the individual ports. The surface currents and the E- and H-field distributions were studied for a better understanding of the polarization mechanism. The measured results of the proposed dual polarized antenna were in accordance with the simulated analysis and showed good performance of the S-parameters and radiation patterns (co-pol and cross-pol), gain, efficiency, front-to-back ratio, half-power beam width) at the resonant frequency. With these features and its compact size, the proposed antenna will be suitable for X-band airborne synthetic aperture radar applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.4
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• pp.683-690
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• 2018

In this paper, a new signal processing technique is proposed for calibrating gain, phase, delay offsets in array antenna based anti-jamming minimum variance distortionless response (MVDR) global-positioning-system (GPS) receivers. The proposed technique estimates gain, phase and delay offsets across the antennas, and compensates for the offsets based on the estimates. A pilot signal with good correlation characteristics is used for accurate estimation of the gain, phase and delay offsets. Based on the cross-correlation, the delay offset is first estimated and then gain/phase offsets are estimated. For fine delay offset estimation and compensation, an interpolation technique is used, and specifically, the discrete Fourier transform (DFT) is employed for the interpolation technique to reduce the computational complexity. The proposed technique is verified through computer simulation using MATLAB. According to the simulation results, the proposed technique can reduce the gain, phaes and delay offset to 0.01 dB, 0.05 degree, and 0.5 ns, respectively.