• Proceedings of the PSK Conference
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• 2002.10a
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• pp.409.1-409.1
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• 2002

For the development of a biocompatible nano-scale drug carrier. hydrophilic polysaccharide pullulan was hydrophobized by the conjugation with fatty acid. The synthesized polymers were characterized by the measurements of fourier transform infrared (FT -IR) spectroscopy and 1H -nuclear magnetic resonance (NMR) spectroscopy. In aqueous solution. hydrophobically modified puliulan was self-assembled and structured into the core-shell type nanoparticles. (omitted)

• Proceedings of the KIEE Conference
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• 2007.11b
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• pp.12-14
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• 2007

A voltage transformer (VT) is used to transform a high voltage into a low voltage as an input for a metering device or a protection relay. VTs use an iron core which maximizes the flux linkage. The primary current of the VT has non-fundamental components caused by the hysteresis characteristics of the iron core. It causes a voltage drop in the winding impedances resulting in the error of the VT. This paper describes a compensation algorithm for the VT. The proposed algorithm can compensate the secondary voltage of VT by calculating the primary current from the exciting current of the hysteresis loop in the voltage transformer. In this paper, the exciting branch was divided into a non-linear core loss resistor and a non-linear magnetizing inductor. The performance of the proposed algorithm was validated under various conditions using EMTP generated data. Test results show that the proposed compensation algorithm can improve the accuracy of the VT significantly.

• Advances in environmental research
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• v.4 no.2
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• pp.69-81
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• 2015

A new magnetite-silica core/shell nanocomposite ($Fe_3O4@nSiO_2@mSiO_2$) was synthesized and functionalized with trimethylchlorosilane (TMCS). The prepared nanocomposite was used for the removal of diesel oil from aqueous media. The characterization of magnetite-silica nanocomposite was studied by X-ray diffraction (XRD), Fourier transform infrared (FTIR), transmission electron microscopy (TEM), surface area measurement, and vibrating sample magnetization (VSM). Results have shown that the desired structure was obtained and surface modification was successfully carried out. FTIR analysis has confirmed the presence of TMCS on the surface of magnetite silica nanocomposites. The low- angle XRD pattern of nanocomposites indicated the mesoscopic structure of silica shell. Furthermore, TEM results have shown the core/shell structure with porous silica shell. Adsorption kinetic studies indicated that the nanocomposite was able to remove 80% of the oil contaminant during 2 h and fit well with the pseudo-second order model. Equilibrium studies at room temperature showed that the experimental data fitted well with Freundlich isotherm. The magnetic property of nanocomposite facilitated the separation of solid phase from aqueous solution.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12A
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• pp.2074-2084
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• 2001

la this paper, a new digital watermarking algorithm using wavelet transform in frequency domain is suggested. The wavelet coefficients of low frequency subband are utilized to embed the watermark, After the original image is transformed using discrete wavelet transform, their coefficients are transformed into efficient1y in Sequency domain. DCT and FFT transforms are utilized in this processing. Watermark image of general image format is transformed using DCT and the hiding watermark into wavelet coefficients is equally distributed in frequency domain. Next, these wavelet coefficients are performed with inverse transform. The detection process of watermark is performed with reverse direction to insertion process. In this paper, we developed core watermark technologies which are a data hiding technology to hide unique logo mark which symbolizes the copyright and a robust protection technology to protect logo data from external attack like as compression, filtering, resampling, cropping. The experimental results show that two suggested watermarking technologies are invisible and robust.

• Journal of the Korean Society of Systems Engineering
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• v.15 no.2
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• pp.98-107
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• 2019

The defense system development process is a process of developing various systems that perform functions in various functional areas such as battlefield awareness, command control, force application, and logistical support. In other words, the defense system development process is a process of developing many systems simultaneously in various functional areas. Various systems developed through this process should be interoperable so that they can be integrated and operated in a joint warfighting environment. To successfully implement this, the US Department of Defense uses the Joint Capability Integrated Development System(JCIDS) for the defense system development, and within this JCIDS processes the Capability Based Assessment(CBA) methodology as its core technology. This CBA methodology transforms the mission activity requirements to functional capability requirements logically and transforms the functional capability requirements to system requirements logically also. Smart City is a city that improves the convenience and quality of life of the citizen by integrates various systems that perform various functions of the city and smarties various functional systems with smart services by using IT technology. In other words, defense system development and smart city development have a common feature of the process of developing many systems simultaneously in various functional areas. In order to address the problem of having to develop many systems simultaneously in each functional area, it is important to logically transform the various mission scenarios into functions and logically transform the functions into systems. Therefore, a joint capability integrated development system and its core methodology, Capability Based Assessment(CBA), can be applied to smart city development. This paper proposes a method for performing a smart city concept design method using the capability based evaluation (CBA) method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.61-68
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• 2005

A chip, which can fast encoder the audio data to AAC (Advanced Audio Coding) LC(Low Complexity) that is MPEG-2 audio standard, has been designed on the basis of a 32 bits DSP core and fabricated with 0.25um CMOS technology. At first, the various optimization methods for implementing the algerian are devised to reduce the memory size and calculation cycles. FFT(Fast Fourier Transform) hardware block is added to the DSP core to get the more reduction of the calculation cycles. The chips has the size of $7.20\times7.20 mm^2$ and about 830,000 equivalent gates, can carry out AAC encoding under 70MIPS(Million Instructions per Second).

• Journal of Korea Game Society
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• v.14 no.4
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• pp.45-52
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• 2014

We cannot load the entire data for high-resolution terrain model to the GPU memory since its size is too big. Out-of-core approaches are commonly used to solve the problem. However, due to limited bandwidth of the secondary storage, it is difficult to render the terrain in real-time. A method that compresses the DEM data with wavelet transform on GPU, and renders the decoded data is suggested. However, it is inefficient since it has to sample the values from textures, convert them to vertices, and generate a mesh periodically. We propose a method to store the approximation coefficients of wavelet compression as vertex attributes and render the terrain by decoding the data on geometric shader. It can reduce the amount of transferring terrain texture since approximation coefficients are given as an attribute of the vertex. Also, it generate meshes without additional upload of terrain texture.

• Geophysics and Geophysical Exploration
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• v.20 no.2
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• pp.72-77
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• 2017

We calculated 3D frequency- and Laplace-domain wavefields using time-domain modeling and Fourier transform or Laplace transform. We adopted OpenACC and GPU for an efficient parallel calculation. The OpenACC makes it easy to use GPU accelerators by adding directives in conventional C, C++, and Fortran programming languages. Accordingly, one doesn't have to learn new GPGPU programming languages such as CUDA or OpenCL to use GPU. An OpenACC program allocates GPU memory, transfers data between the host CPU and GPU devices and performs GPU operations automatically or following user-defined directives. We compared performance of 3D wave propagation modeling programs using OpenACC and GPU to that using single-core CPU through numerical tests. Results using a homogeneous model and the SEG/EAGE salt model show that the OpenACC programs are approximately 53 and 30 times faster than those using single-core CPU.

• Journal of IKEEE
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• v.21 no.4
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• pp.358-367
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• 2017

Advanced Driver Assistance Systems(ADAS), such as Front Collision Warning System (FCWS) are currently being developed. FCWS require high processing speed because it must operate in real time while driving. In addition, a low-power system is required to operate in an automobile embedded system. In this paper, FCWS is implemented in CPU-FPGA architecture in embedded system to enable real-time processing. The lane detection enabled the use of the Inverse Transform Perspective (IPM) and sliding window methods to operate at fast speed. To detect the vehicle, a Convolutional Neural Network (CNN) with high recognition rate and accelerated by parallel processing in FPGA is used. The proposed architecture was verified using Intel FPGA Cyclone V SoC(System on Chip) with ARM-Core A9 which operates in low power and on-board FPGA. The performance of FCWS in HD resolution is 44FPS, which is real time, and energy efficiency is about 3.33 times higher than that of high performance PC enviroment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1778-1784
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• 2016

we improved the performance by parallelizing lane detection algorithms. Lane detection, as a intellectual assisting system, helps drivers make an alarm sound or revise the handle in response of lane departure. Four kinds of algorithms are implemented in order as following, Gaussian filtering algorithm so as to remove the interferences, gray conversion algorithm to simplify images, sobel edge detection algorithm to find out the regions of lanes, and hough transform algorithm to detect straight lines. Among parallelized methods, the data level parallelism algorithm is easy to design, yet still problem with the bottleneck. The high-speed data level parallelism is suggested to reduce this bottleneck, which resulted in noticeable performance improvement. In the result of applying actual road video of black-box on our parallel algorithm, the measurement, in the case of single-core, is approximately 30 Frames/sec. Furthermore, in the case of octa-core parallelism, the data level performance is approximately 100 Frames/sec and the highest performance comes close to 150 Frames/sec.