• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.227-233
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• 2011

This paper presents a small-area ISDB-T time deinterleaver structure. ISDB-T is an mobile TV standard that is widely used in Japan and many South American countries. One of the strong points of the standard is the long interleaving depth, which enhance the communication performance. However, long interleaving requires many delay buffers, in other words many pointer registers. This paper reduces the number of pointer registers with the deinterleaver equivalent transformation. The experimental results show that the area is reduced with the proposed structure.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.221-226
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• 2011

This paper presents a DTMB deinterleaver structure to reduce SDRAM power consumption. DTMB, the Chinese digital TV standard, has a deinterleaver that consists of many long delay buffers. SDRAM is used for this deinterleaver. The proposed structure pairs data and transfer a pair with an SDRAM transfer. With the reduction of the SDRAM operation number, the proposed structure can save the SDRAM power consumption by around 35%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1135-1140
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• 2011

This paper proposes a DTMB deinterleaver structure to reduce the SDRAM power consumption with buffer conversion and the single pointer-register structure. The DTMB deinterleaver with deep interleaving for higher performance consists of long delay buffers allocated on SDRAM. The conventional structure activates a new SDRAM row almost everytime when it reads and writes a datum. In the proposed structure, long buffers are transformed into several short buffers so that the number of row activations is reduced. The single pointer-register structure solves the problem of many pointer-registers. The experimental results show that the SDRAM power consumption can be reduced to around 37% with slight logic area reduction.

• Information and Communications Magazine
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• v.12 no.6
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• pp.88-100
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• 1995

본 고에서는 디지털 위성방송 시스템의 구성요소중 channel부의 구조 및 기능분석을 국내 디지털 DBS를 기준으로 설명하였다. channel부는 channel coding과 modulation 기능을 수행한다. Channel coding은 Reed Solomon code, interleaving, convolutional code를 연집하여 사용하고, modulation은 QPSK와 raised cosine pulse shaping을 한다. 수신기의 channel부는 antenna, LNB, tuner, QPSK 복조기, Viterbi, deinterleaver, RS decoder로 구성되어있다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.6 s.97
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• pp.556-562
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• 2005

In this paper, we propose interleaved super-orthogonal convolutional coded ultra wide-band impulse radio(ISOC-UWB-IR) system, and analyze its performance. The proposed system uses interleaver and deinterleaver to decorrelate the temporal correlation of the fading process and to obtain the diversity gain. We also suggest the three types of interleavers, which are pulse-wise interleaver(PI), pulse sub-group-wise interleaver(PSGI), and pulse group-wise interleaver(PGI). Performance analysis result shows that the interleaving scheme, rather than the code rate of super orthogonal convolutional code(SOC) encoder, affects the performance for the Rayleigh fading channel.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.3
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• pp.125-131
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• 2002

In this paper, a new concatenation scheme of serial concatenated convolutional codes is proposed and the performance analyzed. In the proposed scheme, each of information and parity bits of outer code is entered into inner code through interleaver and deinterleaver. Therefore, the interleaver size is same as the length of input frame. Since the interleaver size of proposed type is reduced to half of the conventional Benedetto type, the interleaver delay time required for iterative decoding is reduced. In addition the multiplexer and demultiplexer are not used in the decoder of the proposed type, the complexity of decoder can be also reduced. As results of simulation, the performance of proposed type shows the better error performance as compared to that of the conventional Benedetto type in case of the same interleaver size. And it can be observed that the difference of BER performance is increased with the increase of Eb/No. In case of the same length of input frame, the proposed type shows almost same performance with Benedetto type despite that the interleaver size is reduced by half.

• Journal of Digital Convergence
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• v.12 no.3
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• pp.269-275
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• 2014

The DAB system was designed to provide CD quality audio and data services for fixed, portable and mobile applications with the required BER below $10^{-4}$. However for the T-DMB system with the video service of MPEG-4 stream, BER should go down $10^{-8}$ by adding FEC blocks which consist of the Reed-Solomon (RS) encoder/decoder and convolutional interleaver/deinterleaver. In this paper we propose two types of turbo coded T-DMB system without altering the puncturing procedure and puncturing vectors defined in the standard T-DMB system for compatibility. One(Type 1) can replace the existing RS code, convolutional interleaver and RCPC code by a turbo code and the other one (Type 2) can substitute the existing RCPC code by a turbo code. Simulation results show that two new turbo coded systems are able to yield considerable performance gain after just 2 iterations. Type 2 system is better than type 1 but the amount of performance improvement is small.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.