• Title/Summary/Keyword: converter optimization

Search Result 130, Processing Time 0.025 seconds

Integrated Planar Transformer Design of 3 kW LDC for Electric Vehicles (전기자동차용 3kW급 LDC를 위한 통합형 플라나변압기 설계)

  • Ramadhan, Ramadhan;Suk, Chaeyoung;Kim, Sangjin;Choi, Sewan;Yu, Byeongu;Park, Sanghun
    • Proceedings of the KIPE Conference
    • /
    • 2020.08a
    • /
    • pp.157-159
    • /
    • 2020
  • This paper presents an optimal planar transformer design of a 3-kW Low voltage DC-DC Converter (LDC) with 3.68 kW/L power density for electric vehicle (xEV) application. The transformer is optimized based on the trade-off between footprint and loss using the proposed figure-of-merit (FOM) based optimization. In order to achieve ZVS under entire load range, an external leakage inductance is added and implemented using the proposed magnetic integration technique. A comparison between non-integrated and integrated magnetic core using finite element analysis (FEA) is presented. The result shows that the integrated core can reduce the core loss up to 35 % and core boxed volume up to 15 % compared to the non-integrated core. Experimental results are also provided to validate the proposed magnetic integration technique.

  • PDF

Design and optimization of thermal neutron activation device based on 5 MeV electron linear accelerator

  • Mahnoush Masoumi;S. Farhad Masoudi;Faezeh Rahmani
    • Nuclear Engineering and Technology
    • /
    • v.55 no.11
    • /
    • pp.4246-4251
    • /
    • 2023
  • The optimized design of a Neutron Activation Analysis (NAA) system, including Delayed Gamma NAA (DGNAA) and Prompt Gamma NAA (PGNAA), has been proposed in this research based on Mevex Linac with 5 MeV electron energy and 50 kW power as a neutron source. Based on the MCNPX 2.6 simulation, the optimized configuration contains; tungsten as an electron-photon converter, BeO as a photoneutron target, BeD2 and plexiglass as moderators, and graphite as a reflector and collimator, as well as lead as a gamma shield. The obtained thermal neutron flux at the beam port is equal to 2.06 × 109 (# /cm2.s). In addition, using the optimized neutron beam, the detection limit has been calculated for some elements such as H-1, B-10, Na-23, Al-27, and Ti-48. The HPGe Coaxial detector has been used to measure gamma rays emitted by nuclides in the sample. By the results, the proposed system can be an appropriate solution to measure the concentration and toxicity of elements in different samples such as food, soil, and plant samples.

Numerical Study on Shape Optimization of a Heaving Hemisphere Wave Energy Converter (상하 운동 반구형 파력 발전기의 최적 형상 조건 수치해석)

  • Kim, Sung-Jae;Koo, Weoncheol;Heo, Kyung-Uk;Heo, Sanghwan
    • Journal of the Korean Society for Marine Environment & Energy
    • /
    • v.18 no.4
    • /
    • pp.254-262
    • /
    • 2015
  • Parametric study on submerged body shape of an oscillating hemisphere point absorber was conducted to predict the optimal relation between radius and draft of the body. As an additional damping due to power takeoff system, the optimal damping same as wave radiation damping was applied to the PTO system to produce the maximum wave power. Body response spectrum and power spectrum were obtained for various peak frequencies on wave spectra. It was found that the maximum power can be generated when the peak frequency of available wave power was 20% greater than that of wave spectrum.

Optimized Design of Low Voltage High Current Ferrite Planar Inductor for 10 MHz On-chip Power Module

  • Bae, Seok;Hong, Yang-Ki;Lee, Jae-Jin;Abo, Gavin;Jalli, Jeevan;Lyle, Andrew;Han, Hong-Mei;Donohoe, Gregory W.
    • Journal of Magnetics
    • /
    • v.13 no.2
    • /
    • pp.37-42
    • /
    • 2008
  • In this paper, design parameters of high Q (> 50), high current inductor for on-chip power module were optimized by 4 Xs 3 Ys DOE (Design of Experiment). Coil spacing, coil thickness, ferrite thickness, and permeability were assigned to Xs, and inductance (L) and Q factor at 10 MHz, and resonance frequency ($f_r$) were determined Ys. Effects of each X on the Ys were demonstrated and explained using known inductor theory. Multiple response optimizations were accomplished by three derived regression equations on the Ys. As a result, L of 125 nH, Q factor of 197.5, and $f_r$ of 316.3 MHz were obtained with coil space of $127\;{\mu}m$, Cu thickness of $67.8\;{\mu}m$, ferrite thickness of $130.3\;{\mu}m$, and permeability 156.5. Loss tan ${\delta}=0$ was assumed for the estimation. Accordingly, Q factor of about 60 is expected at tan ${\delta}=0.02$.

The study of a novel SWRO-PRO hybrid desalination technology (SWRO-PRO 복합해수담수화 신공정기술의 연구)

  • Kim, Jisook;Yeo, Inho;Lee, Wonil;Park, Taeshin;Park, Yonggyun
    • Journal of Korean Society of Water and Wastewater
    • /
    • v.32 no.4
    • /
    • pp.317-324
    • /
    • 2018
  • SWRO-PRO hybrid desalination technology is recently getting more attention especially in large desalination markets such as USA, Middle East, Japan, Singapore, etc. because of its promising potential to recover a considerable amount of osmotic energy from brine (a high-concentration solution of salt, 60,000 - 80,000 mg/L) and also to minimize the impact of the discharged brine into a marine ecosystem. By the research and development of the core technologies of the SWRO-PRO desalination system in a national desalination research project (Global MVP) supported by Ministry of Land, Infrastructure, and Transport (MOLIT) and Korea Agency for Infrastructure Technology Advancement (KAIA), it is anticipated that around 25% of total energy consumption rate (generally 3 to $4kWh/m^3$) of the SWRO desalination can be reduced by recovering the brine's osmotic energy utilizing wastewater treatment effluent as a PRO feed solution and an isobaric pressure exchanger (PX, ERI) as a PRO energy converter. However, there are still several challenges needed to be overcome in order to ultimately commercialize the novel SWRO-PRO process. They include system optimization and integration, development of efficient PRO membrane and module, development of PRO membrane fouling control technology, development of design and operation technology for the system scaling-up, development of diverse business models, and so on. In this paper, the current status and progress of the pilot study of the newly developed SWRO-PRO hybrid desalination technology is discussed.

Design of Timing Register Structure for Area Optimization of High Resolution and Low Power SAR ADC (고해상도 저전력 SAR ADC의 면적 최적화를 위한 타이밍 레지스터 구조 설계)

  • Min, Kyung-Jik;Kim, Ju-Sung;Cho, Hoo-Hyun;Pu, Young-Gun;Hur, Jung;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.47 no.8
    • /
    • pp.47-55
    • /
    • 2010
  • In this paper, a timing register architecture using demultiplexer and counter is proposed to reduce the area of the high resolution SAR type analog to digital converter. The area and digital power consumption of the conventional timing register based on the shift register is drastically increased, as the resolution is increased. On the other hand, the proposed architecture results in reduction of the area and the power consumption of the error correction logic of the SAR ADC. This chip is implemented with 0.18 um CMOS process. The area is reduced by 5.4 times and the digital power consumption is minimized compared with the conventional one. The 12 bits SAR ADC shows ENOB of 11 bits, power consumption of 2 mW, and conversion speed of 1 MSPS. The die area is $1 mm{\times}1mm$.

DC-DC integrated LED Driver IC design with power control function (전력 제어 기능을 가진 DC-DC 내장형 LED Driver IC 설계)

  • Lee, Seung-Woo;Lee, Jung-Gi;Kim, Sun-Yeob
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.21 no.12
    • /
    • pp.702-708
    • /
    • 2020
  • Recently, as LED display systems have become larger, research on effective power control methods for the systems has been in progress. This paper proposes a power control method to minimize power loss due to the difference in LED characteristics for each channel of a backlight unit (BLU) system. The proposed LED driver IC has a power optimization function and detects the minimum headroom voltage for constant current operation of all channels and linearly controls the DC-DC converter output. Thus, it minimizes power consumption due to unnecessary additional voltage. In addition, it does not require a voltage sensing comparator or a voltage generation circuit for each channel. This has a great advantage in reducing the chip size and for stabilization when implementing an integrated circuit. In order to verify the proposed function, an IC was designed using Cadence and Synopsys' design tools, and it was fabricated with a Magnachip 0.35um 5V/40V CMOS process. The experiments confirmed that the proposed power control method controls the minimum required voltage of the BLU system.

A Study on the Optimization of Offsite Consequence Analysis by Plume Segmentation and Multi-Threading (플룸분할 및 멀티스레딩을 통한 소외사고영향 분석시간 최적화 연구)

  • Seunghwan, Kim;Sung-yeop, Kim
    • Journal of the Korean Society of Safety
    • /
    • v.37 no.6
    • /
    • pp.166-173
    • /
    • 2022
  • A variety of input parameters are taken into consideration while performing a Level 3 PSA. Some parameters related to plume segments, spatial grids, and particle size distribution have flexible input formats. Fine modeling performed by splitting a number of segments or grids may enhance the accuracy of analysis but is time-consuming. Analysis speed is highly important because a considerably large number of calculations is required to handle Level 2 PSA scenarios for a single-unit or multi-unit Level 3 PSA. This study developed a sensitivity analysis supporting interface called MACCSsense to compare the results of the trials of plume segmentation with the results of the base case to determine its impact (in terms of time and accuracy) and to support the development of a modeling approach, which saves calculation time and improves accuracy. MACCSense is an automation tool that uses a large amount of plume segmentation analysis results obtained from MUST Converter and Mr. Manager developed by KAERI to generate a sensitivity report that includes impact (time and accuracy) by comparing them with the base-case result. In this study, various plume segmentation approaches were investigated, and both the accuracy and speed of offsite consequence analysis were evaluated using MACCS as a consequence analysis tool. A simultaneous evaluation revealed that execution time can be reduced using multi-threading. In addition, this study can serve as a framework for the development of a modeling strategy for plume segmentation in order to perform accurate and fast offsite consequence analyses.

A Numerical Study on the Optimization of Urea Solution Injection to Maximize Conversion Efficiency of NH3 (NH3 전환효율 극대화를 위한 Urea 인젝터의 분사 최적화에 관한 수치적 연구)

  • Moon, Seongjoon;Jo, Nakwon;Oh, Sedoo;Jeong, Soojin;Park, Kyoungwoo
    • Transactions of the Korean Society of Automotive Engineers
    • /
    • v.22 no.3
    • /
    • pp.171-178
    • /
    • 2014
  • From now on, in order to meet more stringer diesel emission standard, diesel vehicle should be equipped with emission after-treatment devices as NOx reduction catalyst and particulate filters. Urea-SCR is being developed as the most efficient method of reducing NOx emissions in the after-treatment devices of diesel engines, and recent studies have begun to mount the urea-SCR device for diesel passenger cars and light duty vehicles. That is because their operational characteristics are quite different from heavy duty vehicles, urea solution injection should be changed with other conditions. Therefore, the number and diameter of the nozzle, injection directions, mounting positions in front of the catalytic converter are important design factors. In this study, major design parameters concerning urea solution injection in front of SCR are optimized by using a CFD analysis and Taguchi method. The computational prediction of internal flow and spray characteristics in front of SCR was carried out by using STAR-CCM+7.06 code that used to evaluate $NH_3$ uniformity index($NH_3$ UI). The design parameters are optimized by using the $L_{16}$ orthogonal array and small-the-better characteristics of the Taguchi method. As a result, the optimal values are confirmed to be valid in 95% confidence and 5% significance level through analysis of variance(ANOVA). The compared maximize $NH_3$ UI and activation time($NH_3$ UI 0.82) are numerically confirmed that the optimal model provides better conversion efficiency of $NH_3$. In addition, we propose a method to minimize wall-wetting around the urea injector in order to prevent injector blocks caused by solid urea loading. Consequently, the thickness reduction of fluid film in front of mixer is numerically confirmed through the mounting mixer and correcting injection direction by using the trial and error method.

Low Power ADC Design for Mixed Signal Convolutional Neural Network Accelerator (혼성신호 컨볼루션 뉴럴 네트워크 가속기를 위한 저전력 ADC설계)

  • Lee, Jung Yeon;Asghar, Malik Summair;Arslan, Saad;Kim, HyungWon
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.25 no.11
    • /
    • pp.1627-1634
    • /
    • 2021
  • This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛2, power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.