• 한국정보통신학회:학술대회논문집
• /
• 한국정보통신학회 2017년도 춘계학술대회
• /
• pp.529-530
• /
• 2017

Junctionless FET(JLFET)로 구성된 적층형 3차원 인버터의 전기적 상호작용을 연구하였다. Inter Layer Dielectirc (ILD) 두께에 따른 상단 JLFET의 $N_{gate}-N_{gate}$ 정전용량과 전달 컨덕턴스의 특성 변화를 하단 JLFET 게이트 전압에 따라서 조사하였다. 상단과 하단 JLFET 사이 간격이 수십 nm 인 적층형 구조를 사용할 때에 두 트랜지스터의 거리에 따른 AC 전기적인 상호작용을 고려해야 한다.

• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2005년도 추계종합학술대회
• /
• pp.887-890
• /
• 2005

DGMOSFET는 CMOS 스케일링의 확장 및 단채널 효과를 보다 효과적으로 제어할 수 있는 유망란 소자이다. 특히 20nm이하의 도핑되지 않은 Si 채널에서 단채널 효과를 제어하는데 가장 효과적이다. 본 논문에서는 DGMOSFET의 해석학적 전송모델을 제시할 것이다. 단채널 효과를 해석학적으로 분석하기 위해 Subthreshold Swing(SS), 그리고 문턱전압 roll-off(${\Delta}V_{th}$) 등을 이용하였다. 여기서 제시된 모델은 이온방출효과와 source-drain 장벽을 통해 캐리어들의 양자 터널링을 포함하여 해석할 것이다. 여기서 제시된 모델은 gate길이, 채널두께, 게이트 산화막 두께 등을 설계하는데 이용할 것이다.

• 전력전자학회논문지
• /
• 제19권4호
• /
• pp.376-382
• /
• 2014

This paper proposes the pulse width modulation (PWM) control strategy for low-speed operation in the three-level neutral-point-clamped (NPC) inverters based on the bootstrap gate drive circuit. As a purpose of the cost reduction, several papers have paid attention to the bootstrap circuit applied to the three-level NPC inverter. However, the bootstrap gate driver IC cannot generate the gate signal to the IGBT for low-speed operation, because the bootstrap capacitor voltage decreases under the threshold level. For low-speed operation, the dipolar and partial-dipolar modulations can be the effective solution. However, these modulations have drawbacks in terms of the switching loss and THD. Therefore, this paper proposes the PWM control strategy to operate the inverter at low-speed and to minimize the switching loss and harmonics. The experimental results are presented to verify the validity on the proposed method.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
• /
• pp.653-655
• /
• 2003

Using stacked organic gate insulators and active layer of pentacene deposited at elevated temperatures, pentacene-based organic thin-film transistors(OTFTs) with improved electrical characteristics have been fabricated. Stacked PVP(Polyvinylphenol)-polystyrene gate insulators could compensate the demerits and take advantage of the merits of each other [1]. Also, for the better device performance, moderate substrate heating and high deposition rate of pentacene active layer was adopted [2, 3].

• Journal of Power Electronics
• /
• 제16권2호
• /
• pp.769-777
• /
• 2016

This work focuses on current sharing between punch-through insulated gate bipolar transistors (IGBTs) connected in parallel and evaluates the mechanisms that allow overall current balancing. Two different control strategies are presented. These strategies are based on the modification of transistor gate-emitter control voltage V_GE by using an active gate driver circuit. The first strategy relies on the calculation of the average value of the current flowing through all parallel-connected IGBTs. The second strategy is proposed by the authors on the basis of a current cross reference control scheme. Finally, the simulation and experimental results of the application of the two current sharing control algorithms are presented.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1998년도 하계학술대회 논문집 F
• /
• pp.1966-1968
• /
• 1998

This paper describes a gate drive circuit for series connected IGBTs in high voltage applications. The proposed control criterion of the gate circuit is to actively limit the voltages during switching transients, while minimizing switching transient and losses. In order to achieve the control criterion, an analog closed loop control scheme is adopted. The performance of gate drive circuit is examined experimentally by the series connection of three IGBTs with conventional snubber circuits. The experimental results show the voltage balancing by an active control under wide variation in loads and imbalance conditions.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제17권1호
• /
• pp.156-161
• /
• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• 반도체디스플레이기술학회지
• /
• 제14권2호
• /
• pp.41-45
• /
• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2017년도 전력전자학술대회
• /
• pp.598-599
• /
• 2017

In motor application, High efficiency is important. So Design engineer select small gate resistor for lower switching. But There is side effect with small gate resistor. It makes large dv/dt and system request large EMI filter. It makes price increase. This paper introduce about gate drive IC which have solution both of lower loss and EMI issue.

• 대한전자공학회논문지TC
• /
• 제42권3호
• /
• pp.1-8
• /
• 2005

본 논문에서는 3GPP 중계기 및 기지국용 60W급 Doherty 전력증폭기를 설계 및 제작하였다. Doherty 전력증폭기는 효율개선과 고출력 특성이 뛰어나지만 보조증폭기의 구현이 어렵다. 이를 해결하고자 일반적인 Doherty 전력증폭기에 보조증폭기의 Gate 바이어스 조절회로를 첨가한 GCHD(Gate Control Hybrid Doherty) 전력증폭기를 구현하였다. 실험결과 3GPP 동작주파수 대역인 $2.11\~2.17GHz$에서 이득이 62.55 dB이고, PEP 출력이 50.76 dBm, W-CDMA 평균전력 47.81 dBm, 5MHz offset 주파수대역에서 -40.05 dBc의 ACLR 특성을 가졌으며, 각각의 파라미터는 설계하고자 하는 증폭기의 사양을 만족하였다. 특히 GCHD 전력증폭기는 일반전력증폭기에 비해 ACLR에 따른 효율 개선성능이 우수하였다.