• Title/Summary/Keyword: conditional pass

Search Result 10, Processing Time 0.029 seconds

CONDITIONAL GENERALIZED WIENER MEASURES

  • Kang, Soon-Ja
    • Bulletin of the Korean Mathematical Society
    • /
    • v.28 no.2
    • /
    • pp.147-161
    • /
    • 1991
  • In this paper we define the conditional generalized Wiener measure and then express the conditional generalized Wiener integral over this new measure. In particular we consider a conditional expectation of functionals of the generalized Brownian paths under the condition that the paths pass through the given points .xi.$_{1}$, .xi.$_{2}$, .., .xi.$_{n}$ at times t$_{1}$, t$_{2}$, .., t$_{n}$, respectively.ely.

  • PDF

Analysis on Safety Management of Elevator (승강기 안전관리제도의 문제점 분석에 관한 연구)

  • Choi, Gi-Heung
    • Journal of the Korean Society of Safety
    • /
    • v.22 no.6
    • /
    • pp.7-12
    • /
    • 2007
  • This study focuses on the statistical analysis on safety management of elevators. Specifically, frequency and severity of accidents in relation to conditional pass in periodic inspection, maintenance, market surveillance are analysed based on the statistical data and social loss due to poor management is estimated. The results of statistical analysis performed in this study will provide logical basis and future direction for improving the safety management system.

Design of a Low Power 108-bit Conditional Sum Adder Using Energy Economized Pass-transistor Logic(EEPL) (EEPL을 사용한 저 전력 108-bit 조건합 가산기의 설계)

  • 조기선;송민규
    • Proceedings of the IEEK Conference
    • /
    • 1999.11a
    • /
    • pp.363-367
    • /
    • 1999
  • In this paper, a novel 108-bit conditional sum adder(CSA) with Energy Economized Pass-transistor Logic(EEPL) is proposed. A new architecture is adopted, in order to obtain a high speed operation, which is composed of seven modularized 16-bit CMS's and two separated carry generation block. Further a design technique based on EEPL is proposed to reduce the power consumption. With 0.65${\mu}{\textrm}{m}$ single poly, triple metal, 3.3V CMOS process, its operating speed is about 4.95㎱ and the power consumption is reduced in comparison with that of the conventional adder.

  • PDF

Design of a $54{\times}54$-bit Multiplier Based on a Improved Conditional Sum Adder (개선된 조건 합 가산기를 이용한 $54{\times}54$-bit 곱셈기의 설계)

  • Lee, Young-Chul;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.37 no.1
    • /
    • pp.67-74
    • /
    • 2000
  • In this paper, a $54{\times}54$-bit multiplier based on a improved conditional sum adder is proposed. To reduce the multiplication time, high compression-rate compressors without Booth's Encoding, and a 108-bit conditional sum adder with separated carry generation block, are developed. Furthermore, a design technique based on pass-transistor logic is utilized for optimize the multiplication time and the power consumption by about 5% compared to that of conventional one. With $0.65{\mu}m$, single-poly, triple-metal CMOS process, its chip size is $6.60{\times}6.69\;mm^2$ and the multiplication time is 135.ns at a 3.3V power supply.

  • PDF

Trends and Issues in Safety Management of Elevators in Korea

  • Choi, Gi-Heung
    • International Journal of Safety
    • /
    • v.6 no.2
    • /
    • pp.13-16
    • /
    • 2007
  • This study focuses on the trends and issues of improving safety management of elevators in Korea. Frequency and severity of accidents in relation to conditional pass in periodic inspection, maintenance, market surveillance are analyzed based on the statistical data and social cost due to a variety of related fields in managing elevator safety was estimated first. The results of statistical analysis performed in this study will provide logical basis and future direction for improving the safety management system. The role of certification and supervision is particularly addressed to reduce the related accidents and the social cost. The effectiveness of such procedures can be found from the results of simple statistical analysis.

Chinese-clinical-record Named Entity Recognition using IDCNN-BiLSTM-Highway Network

  • Tinglong Tang;Yunqiao Guo;Qixin Li;Mate Zhou;Wei Huang;Yirong Wu
    • KSII Transactions on Internet and Information Systems (TIIS)
    • /
    • v.17 no.7
    • /
    • pp.1759-1772
    • /
    • 2023
  • Chinese named entity recognition (NER) is a challenging work that seeks to find, recognize and classify various types of information elements in unstructured text. Due to the Chinese text has no natural boundary like the spaces in the English text, Chinese named entity identification is much more difficult. At present, most deep learning based NER models are developed using a bidirectional long short-term memory network (BiLSTM), yet the performance still has some space to improve. To further improve their performance in Chinese NER tasks, we propose a new NER model, IDCNN-BiLSTM-Highway, which is a combination of the BiLSTM, the iterated dilated convolutional neural network (IDCNN) and the highway network. In our model, IDCNN is used to achieve multiscale context aggregation from a long sequence of words. Highway network is used to effectively connect different layers of networks, allowing information to pass through network layers smoothly without attenuation. Finally, the global optimum tag result is obtained by introducing conditional random field (CRF). The experimental results show that compared with other popular deep learning-based NER models, our model shows superior performance on two Chinese NER data sets: Resume and Yidu-S4k, The F1-scores are 94.98 and 77.59, respectively.

Design of a High Performance 32$\times$32-bit Multiplier Based on Novel Compound Mode Logic and Sign Select Booth Encoder (새로운 복합모드로직과 사인선택 Booth 인코더를 이용한 고성능 32$\times$32-bit 곱셈기의 설계)

  • Kim, Jin-Hwa;Song, Min-Gyu
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.38 no.3
    • /
    • pp.205-210
    • /
    • 2001
  • In this paper, a novel compound mode logic based on the advantage of both CMOS logic and pass-transistor logic(PTL) is proposed. From the experimental results, the power-delay products of the compound mode logic is about 22% lower than that of the conventional CMOS logic, when we design a full adder. With the proposed logic, a high performance 32$\times$32-bit multiplier has been fabricated with 0.6um CMOS technology. It is composed of an improved sign select Booth encoder, an efficient data compressor based on the compound mode logic, and a 64-bit conditional sum adder with separated carry generation block. The Proposed 32$\times$32-bit multiplier is composed of 28,732 transistors with an active area of 1.59$\times$1.68 mm2 except for the testing circuits. From the measured results, the multiplication time of the 32$\times$32-bit multiplier is 9.8㎱ at a 3.3V power supply, and it consumes about 186㎽ at 100MHz.

  • PDF

Denoise of Astronomical Images with Deep Learning

  • Park, Youngjun;Choi, Yun-Young;Moon, Yong-Jae;Park, Eunsu;Lim, Beomdu;Kim, Taeyoung
    • The Bulletin of The Korean Astronomical Society
    • /
    • v.44 no.1
    • /
    • pp.54.2-54.2
    • /
    • 2019
  • Removing noise which occurs inevitably when taking image data has been a big concern. There is a way to raise signal-to-noise ratio and it is regarded as the only way, image stacking. Image stacking is averaging or just adding all pixel values of multiple pictures taken of a specific area. Its performance and reliability are unquestioned, but its weaknesses are also evident. Object with fast proper motion can be vanished, and most of all, it takes too long time. So if we can handle single shot image well and achieve similar performance, we can overcome those weaknesses. Recent developments in deep learning have enabled things that were not possible with former algorithm-based programming. One of the things is generating data with more information from data with less information. As a part of that, we reproduced stacked image from single shot image using a kind of deep learning, conditional generative adversarial network (cGAN). r-band camcol2 south data were used from SDSS Stripe 82 data. From all fields, image data which is stacked with only 22 individual images and, as a pair of stacked image, single pass data which were included in all stacked image were used. All used fields are cut in $128{\times}128$ pixel size, so total number of image is 17930. 14234 pairs of all images were used for training cGAN and 3696 pairs were used for verify the result. As a result, RMS error of pixel values between generated data from the best condition and target data were $7.67{\times}10^{-4}$ compared to original input data, $1.24{\times}10^{-3}$. We also applied to a few test galaxy images and generated images were similar to stacked images qualitatively compared to other de-noising methods. In addition, with photometry, The number count of stacked-cGAN matched sources is larger than that of single pass-stacked one, especially for fainter objects. Also, magnitude completeness became better in fainter objects. With this work, it is possible to observe reliably 1 magnitude fainter object.

  • PDF

A Study on the Preprocessing Method Using Construction of Watershed for Character Image segmentation

  • Nam Sang Yep;Choi Young Kyoo;Kwon Yun Jung;Lee Sung Chang
    • Proceedings of the IEEK Conference
    • /
    • 2004.08c
    • /
    • pp.814-818
    • /
    • 2004
  • Off-line handwritten character recognition is in difficulty of incomplete preprocessing because it has not dynamic and timing information besides has various handwriting, extreme overlap of the consonant and vowel and many error image of stroke. Consequently off-line handwritten character recognition needs to study about preprocessing of various methods such as binarization and thinning. This paper considers running time of watershed algorithm and the quality of resulting image as preprocessing For off-line handwritten Korean character recognition. So it proposes application of effective watershed algorithm for segmentation of character region and background region in gray level character image and segmentation function for binarization image and segmentation function for binarization by extracted watershed image. Besides it proposes thinning methods which effectively extracts skeleton through conditional test mask considering running time and quality. of skeleton, estimates efficiency of existing methods and this paper's methods as running time and quality. Watershed image conversion uses prewitt operator for gradient image conversion, extracts local minima considering 8-neighborhood pixel. And methods by using difference of mean value is used in region merging step, Converted watershed image by means of this methods separates effectively character region and background region applying to segmentation function. Average execution time on the previous method was 2.16 second and on this paper method was 1.72 second. We prove that this paper's method removed noise effectively with overlap stroke as compared with the previous method.

  • PDF