• KIEAE Journal
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• v.12 no.6
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• pp.77-84
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• 2012

The current architectural design of unit modular has been based on 2D of CAD program, so unit modular character which needs unit information management, as a dried-member system, has no effect on design process. The purpose of this study is We have developed a suitable BIM design process, according to various works of construction, then tried to contribute to supply and activation of the urban-life-housing based on unit modular. The BIM modeling process based on unit modular has been in order of unit combination with preparing manual classification, and, it has been constructed, at construction site, from housing foundation to roof finish by Bottom-up method. At a manufacturing factory, it has been produced in order of 1) grouping materials and parts, 2) fabricating unit boxes, and 3) interference examination of unit boxes, and each order has been classified as housing structure, architecture, plumbing process separately. At a construction site, the fabrication has been done in order of, like as a real housing construction scenario, 1) RC foundation work 2) unit module job-site-fabrication work, 3) roof truss work, 4) plumbing and HVAC work, and 5) housing interior finish work. After modeling process, the interference examination on each work of construction has finally completed modeling. The Unit modular utilizing BIM modeling can make easy housing maintenance through systematic control with preparing manual of unit module information, and securing accurate and speedy construction information. And it will promote design credibility and create maximum effect of unit modular construction method, such as construction period reduction and upgrade of construction quality, etc., through the computer simulation as real as construction environment in cyber space, and with the interfering examination.

• Nuclear Engineering and Technology
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• v.36 no.6
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• pp.528-539
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• 2004

It is essential in commercial reactors that the safety limits imposed on the fuel pellets and fuel clad barriers, such as the linear power density (LPD) and the departure from nucleate boiling ratio (DNBR), are not violated during reactor operations. In order to accurately monitor the safety limits of current reactor states, a detailed three-dimensional (3D) core power distribution should be estimated from the in-core detector signals. In this paper, we propose a calculation methodology for detailed 3D core power distribution, using in-core detector signals and core monitoring constants such as the 3D Coupling Coefficients (3DCC), node power fraction, and pin-to-node factors. Also, the calculation method for several core safety parameters is introduced. The core monitoring constants for the real core state are promptly provided by the core design code and on-line MASTER (Multi-purpose Analyzer for Static and Transient Effects of Reactors), coupled with the core monitoring program. through the plant computer, core state variables, which include reactor thermal power, control rod bank position, boron concentration, inlet moderator temperature, and flow rate, are supplied as input data for MASTER. MASTER performs the core calculation based on the neutron balance equation and generates several core monitoring constants corresponding to the real core state in addition to the expected core power distribution. The accuracy of the developed method is verified through a comparison with the current CECOR method. Because in all the verification calculation cases the proposed method shows a more conservative value than the best estimated value and a less conservative one than the current CECOR and COLSS methods, it is also confirmed that this method secures a greater operating margin through the simulation of the YGN-3 Cycle-1 core from the viewpoint of the power peaking factor for the LPD and the pseudo hot pin axial power distribution for the DNBR calculation.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.19 no.1
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• pp.19-27
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• 2007

Analytical investigation on the performance of a two stage twin rotary compressor for $CO_2$ heat pump water heater system has been carried out. A computer simulation program was made based on analytical models for gas compression in control volumes, leakages among neighboring volumes, and dynamics of moving elements of the compressor. Calculated cooling capacity, compressor input, and COP were well compared to those of experiments over the compressor speeds tested. For the operating condition of suction pressure of 3 MPa, and discharge pressure of 9 MPa, and compressor inlet temperature of $35^{\circ}C$, the compressor efficiency was calculated to be 80.2%: volumetric, adiabatic, and mechanical efficiencies were 88.3%, 93.2%, and 92.7%, respectively. For the present compressor model, volumetric and adiabatic efficiencies of the second stage cylinder were lower by about $6{\sim}7%$ than those of the first stage mainly due to the smaller discharge port at the second stage. Parametric study on the discharge port size showed that the compressor performance could be improved by 3.5% just by increasing the discharge port diameter by 20%.

• Journal of the Korean Solar Energy Society
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• v.23 no.3
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• pp.45-53
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• 2003

This paper presents a study on the power factor improvement of V47- 660 [kW] Wind Turbine Generation System (WTGS) in Jeju wind farm, as a model system in this paper. In this system, the power factor correction is controlled by the conventional method with power condensor banks. Also, this system has only four bank steps, and each one capacitor bank step is cut in every one second when the generator has been cut in. This means that it is difficult to compensate the reactive power exactly according to the variation of them. Actually, model system has very low power factor in the area of low wind speed, which is almost from 4 to 6 [m/s]. This is caused by the power factor correction using power condenser bank. To improve the power factor in the area of low wind speed, we used the static var compensator(SVC) using current controlled PWM power converter using IGBT switching device. Finally, to verify the proposed method, the results of computer simulation using Psim program are presented to support the discussions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1103-1108
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• 2010

In this paper, Frequency Synthesizer which is widely used for FH-SS system is proposed and the experimental results are analyzed. The performance of the DPLL(Digital Phase-Locked-Loop), which is the main part of the Synthesizer is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the DPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. And the experiential results show that the N value of the loop filter is toggled to adjacent N value, which result in phase jitter of the output. It can be resolved by increasing DCO(Digital Controlled oscillator) clock rate.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.9
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• pp.487-494
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• 2004

The multiprocessor system suffers interconnection network contension while exploiting the program's parallelism. A CC-NUMA system based on point-to-point link ring structure is one of the scalable architectures that expand the system bandwidth the number of processors/nodes increases. The dual-ring system is a simple solution to enhance the system performance and scalability by duplicating the links. In ring-based systems, an unbalanced transaction among links makes a hot spot on the interconnection network. In this situation, total system performance and scalability are bound by the hot spot of the links In this paper, I propose a dual-link CC-NUMA system, which alleviates the concentration of transactions among the links. By the simulation results, the proposed system significantly outperforms the single-ring and bidirection dual-ring systems. In addition, the proposed system show better distribution of transactions among the links that achieves an extended scalability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3B
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• pp.209-216
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• 2003

In this paper, we propose ATM switch structure including AAL type 2 switch which can efficiently transmit low-bit rate data, even if the network has many endpoints. We simulate the architecture of ATM switch fabric that is modeled in computer program and analyze the performance according to offered loads. ATM switch proposed in this paper can support cell switching for all types of AAL cells which consist of AAL type 1, AAL type 2, AAL type 3/4, and AAL type 5 cells. We propose two switch fabric methods; One supports the AAL type 2 cell processing per input port, the other global AAL type 2 cell processing for every input port. The simulation results show that the latter is superior to the former. But the former has a merit for easy implementation and extensibility. The proposed ATM switch fabric is widely applicable to mobile communication, narrow band services over ATM network and wireless ATM as well as general ATM switching fabric.

• Journal of Korea Foundry Society
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• v.27 no.1
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• pp.31-35
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• 2007

In order to develop the semi-solid forming technology for magnesium alloy the rheological and thixotropic behavior of Mg alloy slurry with varying shear rates and cooling rates was investigated and simulated with considering the viscosity based on microstructures and processing variables. The viscosity of slurry of Mg alloy (AZ91D) in semi-solid region was exponentially increased with a solid fraction, and was decreased with increasing a shear rate. In order to analyze precisely the rheological behavior, the ANYCAST program modified with the Carreau model and the different heat transfer coefficient between the cast and mold was used to simulate the flow behavior of Mg semi-solid slurry during the injection into a casting mold in a high pressure diecasting machine. The simulated rheological behavior of Mg alloy slurry was matched well with the experimental results.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1471-1481
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• 2014

This paper presents the new power dissipation model of individual switching device in a high-level modular multilevel converter (MMC), which can be mostly used in voltage sourced converter (VSC) based high-voltage direct current (HVDC) system and flexible AC transmission system (FACTS). Also, the voltage balancing method based on sorting algorithm is newly proposed to advance the MMC functionalities by effectively adjusting switching variations of the sub-module (SM). The proposed power dissipation model does not fully calculate the average power dissipation for numerous switching devices in an arm module. Instead, it estimates the power dissipation of every switching element based on the inherent operational principle of SM in MMC. In other words, the power dissipation is computed in every single switching event by using the polynomial curve fitting model with minimum computational efforts and high accuracy, which are required to manage the large number of SMs. After estimating the value of power dissipation, the thermal condition of every switching element is considered in the case of external disturbance. Then, the arm modeling for high-level MMC and its control scheme is implemented with the electromagnetic transient simulation program. Finally, the case study for applying to the MMC based HVDC system is carried out to select the appropriate insulated-gate bipolar transistor (IGBT) module in a steady-state, as well as to estimate the proper thermal condition of every switching element in a transient state.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1371-1378
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• 2009

We propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at program and read mode, and reduces an operation current at read mode by reducing parasitic capacitances existing at both WL and BL. Asynchronous interface, separate I/O, BL SA circuit of digital sensing method are used for a low-power and small-area eFuse OTP memory IP. It is shown by a computer simulation that operation currents at a logic power supply voltage of VDD and at I/O interface power supply voltage of VIO are 349.5${\mu}$A and 3.3${\mu}$A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18${\mu}$m generic process is 300 ${\times}$557${\mu}m^2$.