• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.

• Journal of applied mathematics & informatics
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• v.17 no.1_2_3
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• pp.297-305
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• 2005

In this paper, we study irregular 3D-Arrays with pyramid shapes. Some computation using Maple software and C++ language have been carried out to illustrate some novel and interesting patterns of numbers in these arrays.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.603-607
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• 1988

On this paper, the application of Eiganstructure assignment to flight control system design is presents. Both output feedback and constrained output feedback are considered. The computer implimentation of the algorithm is discussed including the utilization of real arithmetic for complex conjugate eigenvalue. And the example include a stability augementation system, an autopilot decoupled mode control.

• Communications of the Korean Mathematical Society
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• v.20 no.2
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• pp.231-238
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• 2005

In this paper, we study the arithmetic properties of orders in a quaternion algebra over a dyadic local field and we find the mass formula of orders.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.285-288
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• 2008

Most of multimedia processors for 2D/3D graphics acceleration use a lot of integer/floating point arithmetic units. We present a new architecture with an efficient ALU, built in a smaller chip size. It reduces instruction cycles significantly based on a foundation of multi-thread operation, variable length instruction words, dual phase operation, and phase instruction's coordination. We can decrease the number of instruction cycles up to 50%, and can achieve twice better performance.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04a
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• pp.791-794
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• 2002

본 연구는 영상분석에서 이진 영상의 잡음제거 및 에지 검출을 위한 연구로 임펄스 잡음이 존재하는 영상의 잡음 제거는 임펄스가 크거나 잡음 에너지가 상대적으로 작을 때는 기존의 메디언 필터를 이용하여 잡음을 제거하지만 임펄스 잡음과 같지 않는 잡음이 존재하는 경우에는 본 연구에서 제안한 형태학적인 연산을 적용하여 잡음을 제거하고, 에지를 검출하는 방법을 제안한다.

• Journal of the Korea Society of Computer and Information
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• v.17 no.12
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• pp.49-60
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• 2012

In this paper, we propose a hardware design for correction of barrel distortion using the nearest coordinates in the corrected image. Because it applies the nearest distance on corrected image rather than adjacent distance on distorted image, the picture quality is improved by the image whole area, solve the staircase phenomenon in the exterior area. But, because of additional arithmetic operation using design of bilinear interpolation, required arithmetic operation is increased. Look up table(LUT) structure is proposed in order to solve this, coordinate rotation digital computer(CORDIC) algorithm is applied. The results of the synthesis using Design compiler, the design of implementing all processes of the interpolation method with the hardware is higher than the previous design about the throughput, In case of the rear camera, the design of using LUT and hardware together can reduce the size than the design of implementing all processes with the hardware.

• Progress in Superconductivity and Cryogenics
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• v.7 no.1
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• pp.9-12
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• 2005

We have constructed an RSFQ 4-bit Arithmetic Logic Unit (ALU) in a pipelined structure. An ALU is a core element of a computer processor that performs arithmetic and logic operation on the operands in computer instruction words. We have simulated the circuit by using Josephson circuit simulation tools. We used simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in constructing the 4-bit ALU was consisted of three DC current driven SFQ switches and a half-adder. By commutating output ports of the half adder, we could produce AND, OR, XOR, or ADD functions. The circuit size of the 4-bit ALU when fabricated was 3 mm x 1.5 mm, fitting in a 5 mm x 5mm chip. The fabricated 4-bit ALU operated correctly at 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2S
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• pp.701-710
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• 2000

This paper presents a new method for an efficient coding of very low bit-rate color video based on adaptive wavelet transform. Our approach reveals that the coding process works more efficiently if the quantized wavelet coefficients are preprocessed by a mechanism exploiting the redundancies in the wavelet subband structure. Thus, we focuses optimized activity of coding part, and exhaustive overlapped block motion compensation is utilized to ensure coherency in motion compensated error frames, and raised cosine window is applied. The horizontal and vertical components of motion vectors are encoded separately using adaptive arithmetic coding while significant wavelet coefficients are encoded in bit-plane order using adaptive arithmetic coding. On average the proposed codec exceeds H.263 and ZTE in peak signal-to-noise ratio by as much as 2.07 and 1.38dB at 28 kbits, respectively. Fore entire sequence coding, 3DWCVC method is superior to H.263 and ZTE by 0.35 and 0.71dB on average, respectively.