• Journal of electromagnetic engineering and science
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• 제17권1호
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• pp.20-28
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• 2017

A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output transformers with low loss, which is provided by using 2:2 and 2:1 output transformers for the 2 GHz PA and the 5 GHz PA, respectively. In addition, several design issues in the dual-band PA design using WLP technology are addressed, and a design method is proposed. All considerations for the design of dual-band WLP PA are fully reflected in the design procedure. The 2 GHz WLP CMOS PA produces a saturated power of 26.3 dBm with a peak power-added efficiency (PAE) of 32.9%. The 5 GHz WLP CMOS PA produces a saturated power of 24.7 dBm with a PAE of 22.2%. The PA is tested using an 802.11n signal, which satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieved an EVM of -28 dB at an output power of 19.5 dBm with a PAE of 13.1% at 2.45 GHz and an EVM of -28 dB at an output power of 18.1 dBm with a PAE of 8.9% at 5.8 GHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.1003-1006
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• 2005

Vertex shader of GPU in personal computer is advanced in functions as to be half of traditional fixed T&L functions. And, capacity of memory for saving resources to process instructions is unlimited. GPU that can be programmed by programmer is needed for mobile system as well as personal computer. In this paper, we implement software virtual machine for vertex shader using C++ Language. Our goal is designing hardware GPU that can apply to mobile system. The virtual machine consists of nVidia GPU instructions. Input Data to virtual machine is generated by Microsoft fxc compiler. That is to say, Input Data is compiled shader program written in HLSL, Cg, or ASM. The virtual machine will be a reference model for designing hardware GPU and can be used for Testbed to test added or modified instruction.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.499-502
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• 2004

A two-stage Class E power amplifier operated at 2.44GHz is designed in 0.25-$\mu$m CMOS process for Class-l Bluetooth application. The power amplifier employs c1ass-E topology to exploit its soft-switching property for high efficiency. A preamplifter with common-mode configuration is used to drive the output-stage of Class-E type. The amplifier delivers 20-dBm output power with 70$\%$ PAE (power -added-efficiency) at 2-V supply voltage.

• ETRI Journal
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• 제38권5호
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• pp.818-828
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• 2016

This paper proposes a reusable design for the merging process used in three-dimensional High Efficiency Video Coding (3D-HEVC), which can significantly reduce the implementation complexity by eliminating duplicated module redundancies. The majority of inter-prediction coding tools used in 3D-HEVC are utilized through a merge mode, whose extended merging process is based on built-in integration to completely wrap around the HEVC merging process. Consequently, the implementation complexity is unavoidably very high. To facilitate easy market implementation, the design of a legacy codec should be reused in an extended codec if possible. The proposed 3D-HEVC merging process is divided into the base merging process of reusing HEVC modules and reprocessing process of refining the existing processes that have been newly introduced or modified for 3D-HEVC. To create a reusable design, the causal and mutual dependencies between the newly added modules for 3D-HEVC and the reused HEVC modules are eliminated, and the ineffective methods are simplified. In an application of the proposed reusable design, the duplicated reimplementation of HEVC modules, which account for 50.7% of the 3D-HEVC merging process, can be eliminated while maintaining the same coding efficiency. The proposed method has been adopted as a normative coding tool in the 3D-HEVC international standard.

• 복식
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• 제63권4호
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• pp.30-43
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• 2013

This study provides suggestions of cultural product design contents by using the cloud-shaped gong in traditional temple culture in order to find a high value-added approach. The research herein is part of cultural design contents projects embedded with the spiritual value and symbolic connotation of temple culture. This would be meaningful to enhance its degree of utilization. This can also be a way to find a strategic alternative to a high value addition of temple stay and dissemination of temple culture. For the research methodology, literature was reviewed over temple stay and Bulgeonsamul. For motive design and development of cultural product design, both Adobe Illustrator CS3 and Adobe Photoshop CS3 were used as computer design program. The template image of cloud-shaped gong for basic motive design was selected from those available at the domestic temples for accurate depiction of its head and body. Finally, samples were adopted from those temples of Gounsa, Songgwangsa, Guinsa, Hwaeomsa, and Naesosa. For each motive, different colors were applied and ten basic motives were practiced in total. By repeating the process for these motives, three types of textile design were prepared. T-shirt designs used a round neckline as basic form, and it was designed for sleeved and sleeveless styles. Apron designs stressed V-neckline and two types were processed: one for the back seam line and the other for side seam line. Pendants were designed with modern and luxurious image so that so that it could be used in various types of accessories. Designs for the bedding applied pattern design of the motives and this was done in a way that gave the images a sense of stability and splendor.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 B
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• pp.600-602
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• 1998

In this paper, we implement BIST to efficiently test circuits with pipeline architecture and JTAG to control implemented BIST and support board level test. Since implemented BIST is designed to be initialized using new seed, hard-to-detect faults are easily detected. Besides, to optimize area overhead, it uses JTAG instead of BIST controller and modified pipeline register instead of added test pattern generator and signature generator. And, to optimize pin overhead, it uses pins of JTAG. Function and efficiency of implemented BIST is verified by simulation.

• 한국컴퓨터정보학회논문지
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• 제20권10호
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• pp.31-38
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• 2015

In this paper, we propose the ensemble-based classification model which extracts just new data patterns from the streaming-data by using clustering and generates new classification models to be added to the ensemble in order to reduce the number of data labeling while it keeps the accuracy of the existing system. The proposed technique performs clustering of similar patterned data from streaming data. It performs the data labeling to each cluster at the point when a certain amount of data has been gathered. The proposed technique applies the K-NN technique to the classification model unit in order to keep the accuracy of the existing system while it uses a small amount of data. The proposed technique is efficient as using about 3% less data comparing with the existing technique as shown the simulation results for benchmarks, thereby using clustering.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2014년도 추계학술발표대회
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• pp.53-56
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• 2014

Application specific instruction-set processor (ASIP) is a suitable design choice for system designers who seek both flexibility to handle various applications in the domain together with the performance. Successful development of an ASIP, however, requires a software development kit (SDK) to be provided along with the processor. Synopsys Processor Designer is an ASIP development tool, which takes as input a set of files written in a high-level architecture description language called LISA (Language for Instruction Set Architecture), and generates SDK as well as RTL. Recently, they have added support for the generation of LLVM compiler backend, though some manual work is required. In this paper, we introduce some details in porting LLVM compiler to a custom processor architecture in Synopsys Processor Designer.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.1221-1224
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• 2005

In this paper, by using MPEC-4 systems, it is easy to create MPEC-4 file and to design multimedia which it understands. Also, by using a MPEG-Pro it is proposed that the user understood the data transfer and expression etc. easily and it added the focus processing function it will be able to design and to be possible individual learning which is easy with the CD and web program. The effectiveness of this new multimedia courseware using MPEG-4 have been proven by experiments in practical teaching-learning method of courseware

• 한국식품저장유통학회지
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• 제3권2호
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• pp.195-202
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• 1996

The compression strength of the corrugated fiberboard boxes is very important information to the manufacturers and the end users. The computer program being used to design the compression strength of the boxes was developed by using Korean Standards for the corrugated fiberboard box and some other data. The developed computer program could be applied to only the boxes produced according to the Korean Standards. Also this program needs to be revised continuously by the newly added and developed data.