• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.3
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• pp.463-468
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• 2016

The overall performance of multiuser systems significantly depends on how effectively and fairly manage resources shared by them. The efficient resource management strategies are even more important for multimedia users since multimedia data is delay-sensitive and massive. In this paper, we focus on resource allocation based on a game-theoretic approach, referred to as Nash bargaining solution (NBS), to provide a quality of service (QoS) guarantee for each user. While the NBS has been known as a fair and optimal resource management strategy, it is challenging to find the NBS efficiently due to the computationally-intensive task. In order to reduce the computation requirements for NBS, we propose an approach that requires significantly low complexity even when networks consist of a large number of users and a large amount of resources. The proposed approach linearizes utility functions of each user and formulates the problem of finding NBS as a convex optimization, leading to nearly-optimal solution with significantly reduced computation complexity. Simulation results confirm the effectiveness of the proposed approach.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1429-1439
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• 2019

Buck-Boost LLC (BBLLC) converters based on a PWM + phase control strategy are good candidates for high efficiency, high power density and wide input range applications. Nevertheless, they suffer from large computational complexity when it comes to calculating the optimal phase for ZVS of all the switches. In this paper, a method is proposed for a microcontroller unit (MCU) to calculate the optimal phase quickly and accurately. Firstly, a 2-D lookup table of the phase is established with an index of the input voltage and output current. Then, a bilinear interpolation method is applied to improve the accuracy. Meanwhile, simplification of the phase equation is presented to reduce the computational complexity. When compared with conventional curve-fitting and LUT methods, the proposed method makes the best tradeoff among the accuracy of the optimal phase, the computation time and the memory consumption of the MCU. Finally, A 350V-420V input, 24V/30A output experimental prototype is built to verify the proposed method. The efficiency can be improved by 1% when compared with the LUT method, and the computation time can be reduced by 13.5% when compared with the curve-fitting method.

• Electronics and Telecommunications Trends
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• v.36 no.6
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• pp.1-12
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• 2021

As the demand for big data and big data-based artificial intelligence (AI) technology increases, the need for privacy preservations for sensitive information contained in big data and for high-speed encryption-based AI computation systems also increases. Fully homomorphic encryption (FHE) is a representative encryption technology that preserves the privacy of sensitive data. Therefore, FHE technology is being actively investigated primarily because, with FHE, decryption of the encrypted data is not required in the entire data flow. Data can be stored, transmitted, combined, and processed in an encrypted state. Moreover, FHE is based on an NP-hard problem (Lattice problem) that cannot be broken, even by a quantum computer, because of its high computational complexity and difficulty. FHE boasts a high-security level and therefore is receiving considerable attention as next-generation encryption technology. However, despite being able to process computations on encrypted data, the slow computation speed due to the high computational complexity of FHE technology is an obstacle to practical use. To address this problem, hardware technology that accelerates FHE operations is receiving extensive research attention. This article examines research trends associated with developments in hardware technology focused on accelerating the operations of representative FHE schemes. In addition, the detailed structures of hardware that accelerate the FHE operation are described.

• Journal of Ocean Engineering and Technology
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• v.12 no.1
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• pp.10-22
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• 1998

In the present work the elastic-plastic FE formulations using dynamic explicit time integration schemes are used for numerical analysis of a large auto-body panel stamping processes. For analyses of more complex cases with larger and more refined meshes, the explicit method is more time effective than implicit method, and has no convergency problem and has the robust nature of contact and friction algorithms while implicit method is widely used because of excellent accuracy and reliability. The elastic-plastic scheme is more reliable and rigorous while the rigid-plastic scheme require small computation time. In finite element simulation of auto-body panel stamping processes, the roobustness and stability of computation are important requirements since the computation time and convergency become major points of consideration besides the solution accuracy due to the complexity of geometry conditions. The performnce of the dynamic explicit algorithms are investigated by comparing the simulation results of formaing of complicate shaped autobody parts, such as a fuel tank and a rear hinge, with the experimental results. It has been shown that the proposed dynamic explicit elastic-plastic finite element method enables an effective computation for complicated auto-body panel stamping processes.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.347-356
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• 2003

The OCT algorithm needs efficient hardware architecture to compute inner product. The conventional methods have large hardware complexity. Because of this reason. a computation sharing multiplier was proposed for implementing inner product. However, the existing multiplier has inefficient hardware architecture in precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we proposed a new efficient computation sharing multiplier and applied it to implementation of 1-D DCT processor. The comparison results show that the new multiplier is more efficient than an old one when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using the proposed multiplier is more high performance than typical design methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.137-141
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• 2007

This paper proposes a cost-effective architecture design of an angle-of-arrival (AOA) estimator based on the multiple signal identification and classification (MUSIC) algerian in UWB systems adapting Multi-band OFDM (MB-OFDM) techniques with two-receive antennas. In the proposed method, by modifying the equations of algorithm in order to remove the high computational functions, the computation power can be significantly reduced without significant performance degradation. The proposed architecture is designed and verified by Verilog HDL, and implemented into 0.13um CMOS standard cell and Xilinx FPGA circuits for the estimation of hardware complexity and computation power. From the results of the implementations, we can find that the proposed circuits reduces the hardware complexity by about 43% and the estimated computation power by about 23%, respectively, compared to the architecture employing the original MUSIC algorithm.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.6
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• pp.106-113
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• 2003

The modified discrete cosine transform (MDCT) and inverse MDCT (IMDCT) are employed in subband/transform coding schemes as the analysis/synthesis filter bank based on time domain aliasing cancellation (TDAC). And the MDCT and IMDCT are the most computational intensive operations in layer III of the MPEG audio coding standard. In this paper, we propose a new efficient algorithm for the MDCT/IMDCT computation in various audio coding systems. It is based on the MDCT/IMDCT computation algorithm using the discrete cosine transforms (DCTs), and It employs two discrete cosine transform of type II (DCT-II) to compute the MDCT/IMDCT In addition, it takes advantage of ability in calculating the MDCT/IMDCT computation, where the length of a data block Is divisible by 4. The Proposed algorithm in this paper requires less calculation complexity than the existing method does. Also, it can be implemented by the parallel structure, therefore its structure is particularly suitable for VLSI realization

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.487-497
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• 2008

This paper proposes a new adaptive QRD-M algorithm for MIMO systems. The proposed scheme controls the number of survivor paths,0 based on the channel condition at each layer. The original QRD-M algorithm used fixed M at each layer and it needs large M to achieve near-MLD (maximum-likelihood detection) performance. However, using the large M increases the computation complexity. In this paper, we further effectively control M by employing the channel indicator which includes not only the channel gain, but also instantaneous noise information without necessity of SNR measurement. We found that the ratio of the minimum path metric to the second minimum is good reliability indicator for the channel condition. By adaptively changing M based on this ratio, the proposed scheme effectively achieves near MLD performance and computation complexity of the proposed scheme is significantly smaller than the conventional QRD-M algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1047-1054
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• 2004

In this paper, we present two systolic arrays for computing multiplications in CF(2$\^$m/) generated by an irreducible all one polynomial (AOP). The proposed two systolic mays have parallel-in parallel-out structure. The first systolic multiplier has area complexity of O(㎡) and time complexity of O(1). In other words, the multiplier consists of m(m+1)/2 identical cells and produces multiplication results at a rate of one every 1 clock cycle, after an initial delay of m/2+1 cycles. Compared with the previously proposed related multiplier using AOP, our design has 12 percent reduced hardware complexity and 50 percent reduced computation delay time. The other systolic multiplier, designed for cryptographic applications, has area complexity of O(m) and time complexity of O(m), i.e., it is composed of m+1 identical cells and produces multiplication results at a rate of one every m/2+1 clock cycles. Compared with other linear systolic multipliers, we find that our design has at least 43 percent reduced hardware complexity, 83 percent reduced computation delay time, and has twice higher throughput rate Furthermore, since the proposed two architectures have a high regularity and modularity, they are well suited to VLSI implementations. Therefore, when the proposed architectures are used for GF(2$\^$m/) applications, one can achieve maximum throughput performance with least hardware requirements.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.4
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• pp.1504-1526
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• 2018

For uplink multi-user massive MIMO systems, conventional minimum mean square error (MMSE) linear detection method achieves near-optimal performance when the number of antennas at base station is much larger than that of the single-antenna users. However, MMSE detection involves complicated matrix inversion, thus making it cumbersome to be implemented cost-effectively and rapidly. In this paper, we first summarize in detail the state-of-the-art simplified MMSE detection algorithms that circumvent the complicated matrix inversion and hence reduce the computation complexity from ${\mathcal{O}}(K^3)$ to ${\mathcal{O}}(K^2)$ or ${\mathcal{O}}(NK)$ with some certain performance sacrifice. Meanwhile, we divide the simplified algorithms into two categories, namely the matrix inversion approximation and the classical iterative linear equation solving methods, and make comparisons between them in terms of detection performance and computation complexity. In order to further optimize the detection performance of the existing detection algorithms, we propose more proper solutions to set the initial values and relaxation parameters, and present a new way of reconstructing the exact effective noise variance to accelerate the convergence speed. Analysis and simulation results verify that with the help of proper initial values and parameters, the simplified matrix inversion based detection algorithms can achieve detection performance quite close to that of the ideal matrix inversion based MMSE algorithm with only a small number of series expansions or iterations.