• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.6
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• pp.69-74
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• 1983

This paper discussed the high speed complex multiplier based on the Residue Number System (RNS) using combinational logic circuits. In addition, the sigil determination and overflow correction problem in residue addition has been studied. The estimated multiplication time of considered processor were about 53.15 ns.

• Journal of the Korea Society of Computer and Information
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• v.16 no.5
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• pp.101-107
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• 2011

The optimum weight vector is studied to remove interference and jamming signals in adaptive array antenna system. The optimum weight vector is calculated to apply a minimum variance algorithm and cost function in linearly constrained conditions, and accurately estimates target's signal. Adaptive array antenna system is the system which improves signal to noise ratio(SNR) and decreases interference and jammer power. Adaptive array antenna system delays at tap output of antenna array element. Each tap finally makes the complex signal of one in multiplier complex weight. In order to obtain optimum's weight calculation, optimum weight vector is used in this paper. After simulation, resolution is increased below $3^{\circ}$, and sidelobe is decreased about 10 dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.61-69
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• 2009

This paper presents the design results of a low complexity and high throughput LDPC encoder structure. In order to solve the high complexity problem of the LDPC encoder, a simplified matrix-vector multiplier is proposed instead of the conventional complex matrix-vector multiplier. The proposed encoder also adopts a partially parallel structure and performs column-wise operations in matrix-vector multiplication to achieve high throughput. Implementation results show that the proposed architecture reduces the number of logic gates and memory elements by 37.4% and 56.7%, compared with existing five-stage pipelined architecture. The proposed encoder also supports 800Mbps throughput at 40MHz clock frequency which is improved about three times more than the existing architecture.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.309-312
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• 2004

This paper proposes the architecture of UWB OFDM communication system. More high data rate is requested in the 128-point FFT/IFFT of the UWB OFDM communication system than the conventional communication systems. So, the proposed architecture uses pipeline and parallel architecture. For a highly efficient architecture, the optimal clipping power and the input quantization bits are found in simulation. The hardware complexity of the proposed architecture is presented is consideration of Adder, Register and Complex Multiplier.

• Journal of Korean Society for Quality Management
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• v.18 no.2
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• pp.43-53
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• 1990

Mechanical components and structures are a major part of complex systems and the conseguences of their failure can be extremely costly. The ultimate goal of design engineers is to optimize these mechanical and structural design from the point of view of cost, reliability, weight, volume, maintainability and safety. An essential requirement of design optimization is to develop mathematical models for reliability at design stage. This paper is to minimize the cost of resources subject to the constraint that the reliability of the system must meet a specified level. The lagrange multiplier method is used to optimize the lognormal stress-lognormal strength problem. This optimization problem can be reduced to a search problem in one variable. A numerical example is presented to illustrate the optimization problem.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.255-260
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• 1999

This paper shows the design of a high throughput 512-point FFT processor. The performance target of the 512-point FFT processor is to achieve data symbol rate required for OFDM systems. The memory requirement of the 512-point FFT processor is minimized by adopting shuffle memory system. The hardware cost of the 512-point in processor is further reduced by using a complex multiplier with a new strength reduction method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1241-1245
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• 2009

As FFT(Fast Fourier Transform) processor is used in OFDM(Orthogonal Frequency Division Multiplesing) system. According to increase requirement about mobility and broadband, Research about low power and low area FFT processor is needed. So research concern in reduction of memory size and complex multiplier is in progress. Increasing points of FFT increase memory area of FFT processor. Specially, SRU(Signal Reordering Unit) has the most memory in FFT processor. In this paper, we propose a reduced method of memory size of SRU in FFT processor. SRU of 64, 1024 point FFT processor performed implementation by VerilogHDL coding and it verified by simulation. We select the APEX20KE family EP20k1000EPC672-3 device of Altera Corps. SRU implementation is performed by synthesis of Quartus Tool. The bits of data size decide by 24bits that is 12bits from real, imaginary number respectively. It is shown that, the proposed SRU of 64point and 1024point achieve more than 28%, 24% area reduction respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1482-1490
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• 2001

디지털 통신 시스템 및 신호처리 회로의 핵심 연산블록으로 사용될 수 있는 복소수 승산기 코어의 파라미터화된 소프트 IP (Intellectual Property)를 설계하였다. 승산기는 응용분야에 따라 요구되는 비트 수가 매우 다양하므로, 승산기 코어 IP는 비트 수를 파라미터화하여 설계하는 것이 필요하다. 본 논문에서는 복소수 승산기의 비트 수를 파라미터화 함으로써 사용자의 필요에 따라 승수와 피승수를 8-b∼24-b 범위에서 2-b 단위로 선택하여 사용할 수 있도록 하였으며, GUI 환경의 코어 생성기 PCMUL_GEN는 지정된 비트 크기를 갖는 복소수 승산기의 VHDL 모델을 생성한다. 복소수 승산기 코어 IP는 redundant binary (RB) 수치계와 본 논문에서 제안하는 새로운 radix-4 Booth 인코딩/디코딩 회로를 적용하여 설계되었으며, 이를 통해 기존의 방식보다 단순화된 내부 구조와 고속/저전력 특성을 갖는다. 설계된 IP는 Xilinx FPGA로 구현하여 기능을 검증하였다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1992.04a
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• pp.354-358
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• 1992

This paper describes a development of high speed fuzzy inference circuit for the industrialprocesses. The hardware fuzzy inference circuit is developed utilizing a hardware fuzzy inference circuit is developed utilizing a DSP and a multiplier and accumulator chip. To enhance the inference speed, the pipeline disign is adopted at the bottleneck and the general Max-Min inference method is slightly modified as Max-max method. As a results, the inference speed is evaluated to be 100 KFLIPS. Owing to this high speed feature, satisfactory application can be attained for complex high speed motion control as well as the control of multi-input multi-output nonlinear system. As an application, the developed fuzzy inference circuit is embedded to a PLC (Porgrammable Logic Controller) for industrial process control. For the fuzzy PLC system, to fascilitate the design of the fuzzy control knowledge such as membership functions, rules, etc., a MS-Windows based GUI (Graphical User Interface) software is developed.

• Bulletin of the Korean Mathematical Society
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• v.52 no.6
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• pp.1805-1818
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• 2015

In this article, we first consider a linear multiplier fractional q-differintegral operator and then use it to define new subclasses of p-valent analytic functions in the open unit disk U. An attempt has also been made to obtain two new q-integral operators and study their sufficient conditions on some classes of analytic functions. We also point out that the operators and classes presented here, being of general character, are easily reducible to yield many diverse new and known operators and function classes.