• KSII Transactions on Internet and Information Systems (TIIS)
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• 제11권6호
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• pp.3208-3229
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• 2017

Rectification is an essential procedure for simplifying the disparity extraction of stereo matching algorithms by removing vertical mismatches between left and right images. To support real-time stereo matching, studies have introduced several look-up table (LUT)- and computational logic (CL)-based rectification approaches. However, to support high-resolution images, the LUT-based approach requires considerable memory resources, and the CL-based approach requires numerous hardware resources for its circuit implementation. Thus, this paper proposes a multi-level accumulation-based rectification method as a simple CL-based method and its circuit implementation. The proposed method, which includes distortion correction, reduces addition operations by 29%, and removes multiplication operations by replacing the complex matrix computations and high-degree polynomial calculations of the conventional rectification with simple multi-level accumulations. The proposed rectification circuit can rectify $1,280{\times}720$ stereo images at a frame rate of 135 fps at a clock frequency of 125 MHz. Because the circuit is fully pipelined, it continuously generates a pair of left and right rectified pixels every cycle after 13-cycle latency plus initial image buffering time. Experimental results show that the proposed method requires significantly fewer hardware resources than the conventional method while the differences between the results of the proposed and conventional full rectifications are negligible.

• BMB Reports
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• 제50권9호
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• pp.478-483
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• 2017

Budding yeast has dozens of prions, which are mutually dependent on each other for the de novo prion formation. In addition to the interactions among prions, transmissions of prions are strictly dependent on two chaperone systems: the Hsp104 and the Hsp70/Hsp40 (J-protein) systems, both of which cooperatively remodel the prion aggregates to ensure the multiplication of prion entities. Since it has been postulated that prions and the remodeling factors constitute complex networks in cells, a quantitative approach to describe the interactions in live cells would be required. Here, the researchers applied dual-color fluorescence cross-correlation spectroscopy to investigate the molecular network of interaction in single live cells. The findings demonstrate that yeast prions and remodeling factors constitute a network through heterogeneous protein-protein interactions.

• 한국유체기계학회 논문집
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• 제19권2호
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• pp.27-35
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• 2016

The purpose of this study is to develop a method to predict the performance and economics of a micro gas turbine cogeneration system using performance correction curves. The variables of correction curves are ambient temperature, ambient pressure, relative humidity and load fraction. All of the values of correction factors were expressed as relative values with respect to design values at the ISO conditions. Once the correction curves are obtained, system performance can be predicted relatively easily compared to a detailed performance analysis method through a simple multiplication of the correction factors of various variables at any operating conditions. The predicted results using the correction curve method were compared with those by the detailed and more complex performance analysis in a wide operating range, and its feasibility was confirmed. To illustrate the usability of the correction curve method, the results of an economic analysis of a cogeneration system considering varying operating ambient condition and load was presented.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 춘계종합학술대회
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• pp.179-183
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• 2007

본 논문은 Xilinx의 System Generator를 이용하여 저전력용 FSK 수신기를 구현하기 위한 논문이다. 심볼을 검출하기 위해서 16점 FFT를 사용하며, 저전력 효율을 증대하고 신뢰성을 높이기 위해 디지털로 설계한다. 수신기는 1 비트 데이터 처리를 하며 데이터 속도는 10kbps이다. 또한 FFT를 계산할 때 복소 승산을 피하기 위해 CORDIC 알고리듬을 사용하였으며 회전인자에 의한 승산을 회전기로 대체하였다. 수신기의 설계와 시뮬레이션은 먼저 Simulink로 수행하고, FPGA를 구현하기 위해 Xilinx의 System Generator를 사용하여 하드웨어 모델로 변환되며 성능이 확인된다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제13권12호
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• pp.6243-6259
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• 2019

As a foundation of next-generation air transportation systems, automatic dependent surveillance-broadcast (ADS-B) helps pilots and air traffic controllers create a safer and more efficient national airspace system. Owing to the open communication environment, it is easy to insert fake aircraft into the system via spoofing or the insertion of false messages. Efforts have thus been made in academic research and practice in the aviation industry to ensure the security of transmission of messages of the ADS-B system. An identity-based batch verification (IBV) scheme was recently proposed to enhance the security and efficiency of the ADS-B system, but current IBV schemes are often too resource intensive because of the application of complex hash-to-point operations or bilinear pairing operations. In this paper, we propose a lightweight IBV signature scheme for the ADS-B system that is robust against adaptive chosen message attacks in the random oracle model, and ensures the security of batch message verification and against the replaying attack. The proposed IBV scheme needs only a small and constant number of point multiplication and point addition computations instead of hash-to-point or pairing operations. Detailed performance analyses were conducted to show that the proposed IBV scheme has clear advantages over prevalent schemes in terms of computational cost and transmission overhead.

• 한국주조공학회지
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• 제28권6호
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• pp.261-267
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• 2008

In-situ quasicrystalline icosahedral (I) phase reinforced Ti-based bulk metallic glass (BMG) matrix composites have been successfully fabricated by using two distinct thermal histories for BMG forming alloy. The BMG composite containing micron-scale Iphase has been introduced by controlling cooling rate during solidification, whereas nano-scale I-phase reinforced BMG composite has been produced by partial crystallization of BMG. For mechanical properties, micron-scale I-phase distributed BMG composite exhibited lower strength and plasticity compared to the monolithic BMG. On the other hand, nano-scale icosahedral phase embedded BMG composite showed enhanced strength and plasticity. These improved mechanical properties were attributed to the multiplication of shear bands and blocking of the shear band propagation in terms of isolation and homogeneous distribution of nanosize icosahdral phases in the glassy matrix, followed by stabilizing the mechanical and deformation instabilities.

• 대한전자공학회논문지SP
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• 제46권4호
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• pp.157-164
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• 2009

이 논문에서는 OFDM시스템에서 가장 큰 칩 면적을 차지하고 높은 전력을 요구하는 핵심 연산 블록인 FFT에 대하여 파이프라인 Radix-4 MDC 방식의 저면적 구조를 제안하였다. 나비연산기에서 Twiddle factor 복소 곱셈연산을 수행할 때, 기존의 곱셈기를 사용하지 않고 CSD형 계수의 공통패턴을 공유하여 덧셈의 수를 줄일 수 있는 Common sub-expression sharing 방식과 CORDIC 알고리즘을 사용하여 구현 면적을 감소시켰다. 제안구조는 Verilog-HDL을 통해 모델링하고 Synopsys로 논리합성한 결과 기존구조와 비교하여 복소곱셈부는 48.2%감소효과, 전체 FFT구조는 22.1%의 면적 감소효과를 달성하였다. 따라서 제안된 FFT구조는 다양한 크기의 FFT를 사용하는 OFDM용 시스템에 효율적으로 사용될 수 있는 구조임을 보였다.

• 대한임베디드공학회논문지
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• 제12권1호
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• pp.11-18
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• 2017

Finite field arithmetic has been extensively used in error correcting codes and cryptography. Low-complexity and high-speed designs for finite field arithmetic are needed to meet the demands of wider bandwidth, better security and higher portability for personal communication device. In particular, cryptosystems in GF($2^m$) usually require computing exponentiation, division, and multiplicative inverse, which are very costly operations. These operations can be performed by computing modular AB multiplications or modular $AB^2$ multiplications. To compute these time-consuming operations, using $AB^2$ multiplications is more efficient than AB multiplications. Thus, there are needs for an efficient $AB^2$ multiplier architecture. In this paper, we propose a low latency Montgomery $AB^2$ multiplier using redundant representation over GF($2^m$). The proposed $AB^2$ multiplier has less space and time complexities compared to related multipliers. As compared to the corresponding existing structures, the proposed $AB^2$ multiplier saves at least 18% area, 50% time, and 59% area-time (AT) complexity. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as exponentiation, division, and multiplicative inverse.

• 산업경영시스템학회지
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• 제11권18호
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• pp.7-15
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• 1988

This study is concerned with selecting mutually dependent quality improvement alternatives with resource constraints. These qualify improvement alternatives art different fro the tradition at alternatives which are independent from each other. In other words, selection of any improvement alternative requires other related specific improvement. Also the overall product quality in a multi stage manufacturing process is characterized by a complex multiplication method rather than a simple addition method which dose not allow to solve a linear knapsack problem despite its popularity in the traditional study. This study suggests a non-linear integer programming model for selecting mutually dependent quality improvement alternatives in multi-stage manufacturing process. In order to apply the model to selecting alternatives. This study also suggests a heuristic mode1 based on a dynamic programming model which is more practical than the non-linear integer programming model. The logic of the heuristic model enables 1) to estimate improvement effectiveness values on all improvement alternatives specifically defined for this study. 2) to arrange the effectiveness values in a descending order, and 3) to select the best one among the alternatives based on their forward and backward linkage relationships. This process repeats to selects other best alternatives within the resource constraints. This process is presented in a Computer programming in Appendix A. Alsc a numerical example of model application is presented in Chapter 4.

• 한국정보통신학회논문지
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• 제12권8호
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• pp.1488-1494
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• 2008

본 논문은 대역폭에 제약을 받지 않는 우주 통신용에 사용할 목적으로 도플러에 강인한 저 전력 비동기 FSK 수신기를 FPGA로 구현한 논문이다. 사용한 비동기 FSK 수신기는 심볼 검출을 하기 위해 16점 FFT를 이용하며 데이터의 주 속도는 10kbps이고 도플러에 강인하고 전력 효율과 신뢰성을 얻기 위해 디지털 회로로 설계된다. 또한 CORDIC 알고리듬을 이용하여 FFT 연산 시 사용되는 복소 승산을 가산기 및 천이기로 대체하여 저전력화 하였다. 설계 시스템의 검증을 하기 위해 먼저 Simulink로 시뮬레이션 하여 성능을 확인하고Xilinx사의 System Generator를 이용하여 FPGA 구현하여 성능을 비교 검증하였다. 결과적으로 Simulink 결과와 FPGA 구현 결과가 표6과 표7에 의해 잘 일치함을 확인하였다.