• Journal of IKEEE
• /
• v.13 no.4
• /
• pp.63-68
• /
• 2009

The power management integrated circuit(PMIC) for CCD image sensor is presented in this study. A CCD image sensor is very sensitive against temperature. The temperature, that is heat, is generally generated by the PMIC with low efficiency. Since the generated heat influences performance of CCD image sensor, it should be minimized by using a PMIC which has a high efficiency. In order to develop the PMIC with high efficiency, the input stage is designed with synchronous type step down DC-DC converter. The operating range of the converter is from 5V to 15V and the converter is controlled using PWM method. The PWM control circuit consists of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit. The saw-tooth generator is designed with 1.2MHz oscillation frequency. The comparator is designed with the two stages OP Amp. And the error amplifier has 40dB DC gain and $77^{\circ}$ phase margin. The output of the step down converter is connected to input stage of the charge pump. The output of the charge pump is connected to input of the LDO which is the output stage of the PMIC. Finally, the PMIC, based on the PWM control circuit and the charge pump and the LDO, has output voltage of 15V, -7.5V, 3.3V and 5V. The PMIC is designed with a 0.35um process.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.4
• /
• pp.781-788
• /
• 2017

This paper proposes a new algorithm for comparing amplitude between multiple digital input signals and its digital logic architecture. After simultaneously comparing multiple inputs, the proposed algorithm can provide the information of the largest (or smallest) value among them by using a simple digital logic function. The drawback of the method is to increase hardware resource. To overcome this we propose a reuse method of the overlapped logic operation. The proposed method focuses on enhancing the operational clock frequency, in other words decreasing combinational delay time. After implementing the comparing method with HDL (hardware description language), we experiment on it with environment of Cyclone III EP3C40F324A7 FPGA of Altera Inc. In case of 4 input signals, it can increase the operational speed as mush as 1.66 times with 1.20 times the hardware resource. In case of 8, it can also have 2.29 times the clock frequency and 2.15 times the hardware resource.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.26 no.11
• /
• pp.1020-1026
• /
• 2015

In this paper, the design of longitudinal shunt slot array monopulse antenna in the broad wall of waveguide for Ka band millimeter-wave seeker, Dip-Brazing method for fabrication and experiment results are presented. The proposed antenna consists of radiating slots by using Elliot's array synthesis procedure, probe-exciting feed structure for improving the return loss bandwidth and monopulse comparator. Element weigthings in the array have been calculated by continuous Taylor aperture distribution. Also, the simulation tool has been used to characterize the individual isolated slot, which has subsequently been used in Elliot's method to design the slot array efficiently. The designed antenna is fabricated using Dip-Brazing method. The gain of measured antenna is 28.4 dBi. Antenna beamwidth and side lobe levels are similar to the design result we expect.

• ETRI Journal
• /
• v.26 no.6
• /
• pp.520-534
• /
• 2004

As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

• Journal of IKEEE
• /
• v.22 no.1
• /
• pp.87-92
• /
• 2018

Like CPUs, regular expression processors that perform regular expression pattern matching using instructions have been proposed recently. Of these, only REMPc provides features for character class matching. In this paper, we propose an architecture for efficient character class matching in a regular expression processor, which use character class bitmap format in a instruction operand field and implement the hard-wired character class comparator for several frequently used character classes. Using the proposed method, most of the character classes used in Snort rule can be represented by an operand or an instruction. Thus, character class matching can be performed more efficiently in the proposed archiecture than in REMPc.

• Journal of Sensor Science and Technology
• /
• v.19 no.1
• /
• pp.1-7
• /
• 2010

Electrostatic capacitance measurement method in a fine hose was proposed, in which two ring-type electrodes were disposed on the hose in the direction of fluid flow instead of the conventional face-to-face electrodes. With the proposed electrode structure, we realized a Ringer's solution exhaustion detector for an IV(invasive vein) injection set. On a 4 mm-diameter hose of IV set, we disposed two ring-type electrodes of 10 mm width at a distance of 5 mm each other and obtained 0.72 pF and 2.51 pF for air and 10 % dextrose Ringer's solution in the hose, respectively. The capacitance between the two electrodes varied with the hose-wraparound coverage of electrode as well as the width of electrode and the distance between the electrodes. For hose-wraparound electrode coverage of 75 %, the capacitance varied from 0.62 pF to 1.98 pF with the Ringer's solution level between the two electrodes. A charge amplifier converted the capacitance. variation into electric signal and a comparator was used to detect whether Ringer's solution was exhausted or not. The result was delivered to a host using a RF transmitter with 320 MHz carrier frequency.

• Transactions on Electrical and Electronic Materials
• /
• v.14 no.5
• /
• pp.235-241
• /
• 2013

A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.

• Journal of the Korean Society of Fisheries and Ocean Technology
• /
• v.15 no.2
• /
• pp.55-60
• /
• 1979

The forming and design method of single power factor meter is suggested and the sensitive phase angle detect circuit of current and voltage of load was dealt with. In this paper, in order to control and detect of phase angle of the current and voltage, operational amplifier comparator circuit and R-C phase shift circuit was used, and to detect the controlled voltage wave form, the transister chopper pair circuit was used. The test result of this power factor meter was good and reliable at the full range of power factor.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.26 no.6
• /
• pp.87-93
• /
• 2012

In this paper, we propose an analog-to-digital converter to set the address of a I2C slave chip. The proposed scheme converts a fixed voltage between 0 and VDD to the digital value which can be used as the address of the slave chip. The rising time and the falling time are measured with digital counter in a serially connected RC circuit, while the circuit is being charged and discharged with the voltage to be measured. The ratio of the two measured values is used to get the corresponding digital value. This scheme gives a strong point which is to be implementable all the parts except comparator using digital logic. Although the method utilizes RC circuit, it has no relation with the RC value if the quantization error is disregarded. Experimental result shows that the proposed scheme gives 32-level resolution thus it can be used to configure the address of the I2C slave chip.

• Journal of Electrical Engineering and Technology
• /
• v.1 no.1
• /
• pp.63-72
• /
• 2006

The purpose of this raper is to address the negative impedance instability in DC/DC converters. We present the negative impedance instability of PWM DC/DC converters loaded by constant power loads (CPLs). An approach to design digital controllers for DC/DC converters Is presented. The proposed method, called Power Alignment control technique, is applied to DC/DC step-down choppers operating in continuous conduction or discontinuous conduction modes with CPLs. This approach uses two predefined state variables instead of conventional pulse width modulation (PWM) to regulate the output voltage. A comparator compares actual output voltage with the reference and then switches between the appropriate states. It needs few logic gates and comparators to be implemented thus, making it extremely simple and easy to develop using a low-cost application specific integrated circuit (ASIC) for converters with CPLs. Furthermore, stability of the proposed controllers using the small signal analysis as well as the second theorem of Lyapunov is verified. Finally, simulation and analytical results are presented to describe and verify the proposed technique.