• Journal of IKEEE
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• v.17 no.2
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• pp.176-181
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• 2013

This paper presents a CMOS impulse radio ultra-wideband (IR-UWB) receiver implemented using IBM 0.13um CMOS technology for inner/inter-chip wireless interconnection. The IR-UWB receiver is based on the non-coherent architecture which removes the complexity of RF architecture (such as DLL or PLL) and reduces power consumption. The receiver consists of three blocks: a low noise amplifier (LNA) with active balun, a correlator, and a comparator. Simulation results show the die area of the IR-UWB receiver of 0.2mm2, a power gain (S21) of 12.5dB, a noise figure (NF) of 3.05dB, an input return loss (S11) of less than -16.5dB, a conversion gain of 18dB, a NFDSB of 22. The receiver exhibits a third order intercept point (IIP3) of -1.3dBm and consumes 22.9mW of power on the 1.4V power supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.989-998
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• 2012

A ratio type of capacitance measurement circuit is proposed to measure an extremely small value of the fF capacitance on this paper. This measurement circuit is formed with a switched-capacitor integrator, a comparator, and logic circuit blocks to control the switches. It converts the measured ratio value between the known value of on-chip capacitor and the unknown value of capacitor to the digital signal. The fF capacitance with minimized error can be obtained by calculating this ratio. This proposed circuit is designed with standard CMOS $0.18{\mu}m$ process, and various HSpice simulations prove that this capacitance measurement circuit is able to measure the capacitance under 5fF with less than ${\pm}0.3%$ error rate.

• Journal of Power Electronics
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• v.15 no.1
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• pp.10-17
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• 2015

A quasi-constant on-time controlled buck front end in combined discontinuous conduction mode and boundary conduction mode is proposed to improve power factor (PF).When instantaneous AC input voltage is lower than the output bus voltage per period, the buck converter turns into buck-boost converter with the addition of a level comparator to compare input voltage and output voltage. The gate drive voltage is provided by an additional oscillator during distortion time to eliminate the cross-over distortion of the input current. This high PF comes from the avoidance of the input current distortion, thereby enabling energy to be delivered constantly. This paper presents a series analysis of controlling techniques and efficiency, PF, and total harmonic distortion. A comparison in terms of efficiency and PF between the proposed converter and a previous work is performed. The specifications of the converter include the following: input AC voltage is from 90V to 264V, output DC voltage is 80V, and output power is 94W.This converter can achieve PF of 98.74% and efficiency of 97.21% in 220V AC input voltage process.

• Journal of Power Electronics
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• v.10 no.2
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• pp.115-124
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• 2010

In this paper, a simple yet efficient auto mode-hop ripple control structure for buck converters with light load operation enhancement is proposed. The converter, which operates under a wide range of input and output voltages, makes use of a state-dependent hysteretic comparator. Depending on the output current, the converter automatically changes the operating mode. This improves the efficiency and reduces the output voltage ripple for a wide range of output currents for given input and output voltages. The sensitivity of the output voltage to the circuit elements is less than 14%, which is seven times lower than that for conventional converters. To assess the efficiency of the proposed converter, it is designed and implemented with commercially available components. The converter provides an output voltage in the range of 0.9V to 31V for load currents of up to 3A when the input voltage is in the range of 5V to 32V. Analytical design expressions which model the operation of the converter are also presented. This circuit can be implemented easily in a single chip with an external inductor and capacitor for both fixed and variable output voltage applications.

• The Transactions of the Korea Information Processing Society
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• v.4 no.8
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• pp.2120-2132
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• 1997

A layout automation system for analog integrated circuits is proposed. The implemented system performs full-custom analog layout under the analog layout constraints. In order to overcome the demerits of conventional analog layout systems, parameterized module library is proposed. The system can support complex analog layout modules, resulting in a maximum expandability of the system. Moreover, modified dynamic multi-path algorithm is developed by enhancing the conventional Dijkstra algorithm. Several benchmark circuits such as comparator, op amp, and filter was tested by the system. Layout results compared to OPASYN show well-merging layout and interdigitized layout module.

• Smart Media Journal
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• v.5 no.3
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• pp.49-53
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• 2016

Related researches are progressing that method of non-contact method using the electromagnetic field on the human body by detecting the motion recognition signal is the limitations of time and space, so less than the existing systems. In this paper, we designed the circuit system that can implement the hardware that can detect the electric field signal of the human body non-contact method to increase the recognition rate to screen this digital waveform. The PCB design Used to automatically increase of composition of the circuit and the linkage of the comparator digital waveform with circuit simulation of the system. At same time for evaluate the characteristics of the whole circuit system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.421-424
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• 2017

This paper describes a full-wave rectifiers for energy harvesting circuit using vibration detector. The designed circuit operates only when the vibration is detected through the vibration detector and the active diode. When there is no vibration, the comparator is turned off to prevent leakage of energy stored in the $C_{STO}$. The energy stored in the capacitor is used to drive the level converter and the active diode. The energy stored in the capacitor is supplied to an active diode designed as an output power. The vibration detector is implemented with Schmitt Trigger and Peak Detector with Hysteresis function. The proposed circuit is designed in a CMOS 0.35um technology and its functionality has been verified through extensive simulations. The designed chip occupies $590{\mu}m{\times}583{\mu}m$.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.5
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• pp.485-490
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• 2004

This paper presents a new interpolation algorithm for measuring high resolution position information which is prepared to a nino servo control motor using analog quadrature encoder. In the past, there are large capacity of memory(ROM or RAM) and two high price and resolution A/D(Analog-to-Digital Converter) for sensing two quadrature signals from a analog sinusoidal encoder interpolation. But high resolution of position from sinusoidal encoder can be obtained by using only small capacity of memory, one A/D converter and comparator. Experimental results show that the proposed algorithm is useful for measuring high resolution position.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.3
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• pp.873-879
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• 2010

In this paper, MPEG2(Moving Picture Expert Group 2) image data video decoding technique is presented, it is Huffman decoding method and fractal image method which is very complexive algorithm and have too much times to implement this method. This have defect of overlap decoding and transport work because of impossible to represent objective value of resemblance. The proposed method was calculated the mathematical absolute image resemblance and simplify the moving picture process to reducing the step of moving picture codefying. The results show that smoothed moving picture compared recent methods.

• Journal of Power Electronics
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• v.15 no.4
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• pp.1131-1138
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• 2015

This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.