• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.731-736
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• 2017

In this paper, we propose a simplified tag collection algorithm to improve the performances of ISO/IEC 18000-7, which is a standard for an active RFID system. The proposed algorithm modifies the collection command that enables to start a tag collection round. The modified collection command includes the results of the listen period response for the previous collection round. Tags that receive the collection command check the collision status for their responses. If there is no collision, tags transmit their additional data and go into the sleep mode without the point-to-point read command and sleep command. A collection round for the standard consists of a collection command and response, a read command and response, and sleep command. On the other hand, in the proposed algorithm, a collection round consists of a collection command and response. The simulation results showed that the proposed algorithm can improve the identification delay about 16% compared with the standard when the number of tags are 300.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.111-118
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• 2008

In this paper, novel latch-up prevention method that employs power-up sequential switches has been proposed to relieve latch-up problem in liquid crystal display (LCD) driver ICs. These sequential switches are inserted in the 2'nd and 3'rd boosting stages, and are used to short the emitter-base terminals of parasitic p-n-p-n circuit before relevant boosting stages are activated during power-up sequence. To verily the performance of the proposed method, test chips were designed and fabricated in a 0.13-um CMOS process technology. The measurement results indicated that, while the conventional LCD driver If entered latch-up mode at $50^{\circ}C$ accompanying a significant amount of excess current, the driver IC adopting the proposed method showed no latch-up phenomenon up to $100^{\circ}C$ and maintained normal current level of 0.9mA.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.4
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• pp.1-7
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• 1999

The demands for the various type of directional coupler, which is for the sampling of the signal levels in mobile communication baseband or transceiver systems, are growing. The proposed dual directional coupler, which has three parallel coupled transmission lines, can provide the dual coupling and good isolation characteristics between the coupling ports. In this paper, the novel analysis method and the design equation of even and odd mode for the dual directional coupler, which is employing the asymmetrically coupled transmission lines, are proposed. Using the proposed method, the dual directional coupler for PCS system has been designed and fabricated. We obtained the desired coupling value and the high directivity of 40dB. Measured results show the validity of this design method.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.4
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• pp.28-34
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• 2000

In this paper, a continuous-time filter for low voltage and high frequency applications using fully-balanced current integrators is presented. As the balanced structure of integrator circuits, the designed filter has improved noise characteristics and wide dynamic range since even-order harmonics are cancelled and the input signal range is doubled. Using complementary current mirrors, bias circuits are simplified and the cutoff frequency of filters can be controlled easily by a single DC bias current. As a design example, the 3rd-order lowpass Butterworth filter with a leapfrog realization is designed. The designed fully-balanced current-mode filter is simulated and examined by SPICE using 0.65${\mu}{\textrm}{m}$ CMOS n-well process parameters. The simulation results show 50MHz cutoff frequency, 69㏈ dynamic range with 1% total harmonic distortion(THD), and 4㎽ power dissipation with a 3V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.18-26
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• 1999

Recently, various simplified simulation techniques such as firite-difference beam propagation method and non-orthogonal coupled-mode theory have proposed to analyze the optical characteristics of tapered directional couplers supported by the coupling of two propagating modes. Although these approaches are often in sufficiently accurate, they do not provide the detailed solutions encountered in the analysis of tapered guiding structures. For this purpose, we introduce and utilize a newly developed modal transmission-line theory to analyze rigorously power transfer of the directional coupler. The numerical result reveals that the propagation constants of even and odd modes converge to a single value as increasing the spacer thickness between two symmetric tapered guides. Furthermore, 97% of the power incident into a guiding channel is transmitted to the other channel at the tapered angle ${\theta}=0.1^{\circ}$, and the efficiency of power transfer decreases dramatically as increasing the angle.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1184-1189
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• 2004

A new schematic of quadrature voltage controlled oscillator(QVCO) is designed and fabricated. To obtain quadrature characteristic and low phase noise simultaneously, two differential VCOs are forced to un in quadrature mode by using coupling amplifier with a source degeneration resistor, which is optimized to obtain quadrature accuracy with minimum phase noise degradation. The designed QVCO was fabricated in standard CMOS technology. The measured performance showed the phase noise of below -120 dBc/Hz at 1 MHEz frequency offset, tuning bandwidth of 210 MHz from 2.34 GHz to 2.55 GHz with a tuning voltage varying form 0 to 1.8 V Quadrature error of 0.5 degree and amplitude error of 0.2 dB was measured with conjunction with low-lF mixer. The fabricated QVCO requires 19 mA including 5 mA in the VCO core part fiom a 1.8 V supply.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.14-24
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• 2010

Because WSNs operate with limited resources of sensor nodes, its life is extended by cluster-based routing methods. In this study, we use data on direction, distance, density and residual energy in order to maximize the energy efficiency of cluster-based routing methods. Through this study, we expect to minimize the frequency of isolated nodes when selecting a new cluster head autonomously using information on the direction of the upper cluster head, and to reduce energy consumption by switching sensor nodes, which are included in both of the new cluster and the previous cluster and thus do not need to update information, into the sleep mode and updating information only for newly included sensor nodes at the setup phase using distance data. Furthermore, we enhance overall network efficiency by implementing secure and energy-efficient communication through key management robust against internal and external attacks in cluster-based routing techniques. This study suggests the modified cluster head selection scheme which uses the conserved energy in the steady-state phase by reducing unnecessary communications of unchanged nodes between selected cluster head and previous cluster head in the setup phase, and thus prolongs the network lifetime and provides secure and equal opportunity for being cluster head.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.30-35
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• 2009

In this paper, we propose the flexible design architecture for a continuous packet connectivity (CPC) Protocol among additional features of 3GPP HSPA+. In order to meet a practical intellectual property (IP) reuse and the developing time reduction design goals, we utterly take a CPC protocol into account to be realized by reusing digital signal processor (DSP) IP of the proven high speed packet access (HSPA) platform with the minimum hardware modification and addition. Based on the Teak series DSP, the proposed CPC protocol is divided into discontinuous transmit and receive mode, CPC manager, and interface with the proven HSPA platform. According to the regularized verification flow for wireless cellular communication applications, the proposed CPC protocol has been verified in various test scenarios.

• The Journal of Korean Association of Computer Education
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• v.14 no.6
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• pp.1-10
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• 2011

Since IT technology grow rapidly, our ethic of consciousness has become big issue with adverse effect. Many scholar has discussed and tired to solve this problem, but it is still helpless to fix. Therefor in this paper, author will not suggest the solution, but will present model list of adverse effects and cases to prevent accidents. The model list of adverse effects, what author will present is about media addiction, harmful content, cyber-violence, right infringement, cyber terror and decision obstacle. This model list is made by primary and secondary survey. This model will show adverse effect of present day, but also will show future adverse effects that can be prevent. Through out this paper, this model list could use for education plan.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.167-173
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• 2015

This paper presents a study on the Full-HD HEVC(High Efficiency Video Coding) encoder IP(Intellectual Property) design. The designed IP is for HEVC main profile 4.1, and performs encoding with a speed of 60 fps of full high definition. Before hardware and software design, overall reference model was developed with C language, and we proposed a parallel processing architecture for low-power consumption. And also we coded firmware and driver programs relating IP. The platform for verification of developed IP was developed, and we verified function and performance for various pictures under several encoding conditions by implementing designed IP to FPGA board. Compared to HM-13.0, about 35% decrease in bit-rate under same PSNR was achieved, and about 25% decrease in power consumption under low-power mode was performed.