• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.4
• /
• pp.427-435
• /
• 2014

Segmented-channel MOSFETs (SegFETs) can achieve both good performance and variation robustness through the use of $HfO_2$ (a high-k material) to create the shallow trench isolation (STI) region and the very shallow trench isolation (VSTI) region in them. SegFETs with both an HTI region and a VSTI region (i.e., the STI region is filled with $HfO_2$, and the VSTI region is filled with $SiO_2$) can meet the device specifications for high-performance (HP) applications, whereas SegFETs with both an STI region and a VHTI region (i.e., the VSTI region is filled with $HfO_2$, and the STI region is filled with $SiO_2$) are best suited to low-standby power applications. AC analysis shows that the total capacitance of the gate ($C_{gg}$) is strongly affected by the materials in the STI and VSTI regions because of the fringing electric-field effect. This implies that the highest $C_{gg}$ value can be obtained in an HTI/VHTI SegFET. Lastly, the three-dimensional TCAD simulation results with three different random variation sources [e.g., line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV)] show that there is no significant dependence on the materials used in the STI or VSTI regions, because of the predominance of the WFV.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.11
• /
• pp.130-137
• /
• 2013

This paper presents analog front-end(AFE) circuits for bio-potential measurement. The proposed AFE is composed of IA(instrument amplifier), BPF(band-pass filter), VGA(variable gain amplifier) and SAR(successive approximation register) type ADC. The low gm(LGM) circuits with current division technique and Miller capacitance with high gain amplifier enable IA to implement on-chip AC-coupling without external passive components. Spilt capacitor array with capacitor division technique and asynchronous control make the 12-b ADC with low power consumption and small die area. The total current consumption of proposed AFE is 6.3uA at 1.8V.

• Proceedings of the Korean Society of Propulsion Engineers Conference
• /
• 1994.11a
• /
• pp.21-26
• /
• 1994

Conventional electroexplosive devices (EED) commonly use a very small metal bridgewire to ignite explosive materials i.e. pyrotechnics, primary and secondary explosives. The use of semiconductor devices to replace “hot-wire” resistance heating elements in automotive safety systems pyrotechnic devices has been under development for several years. In a typical 1 amp/1 watt electroexplosive devices, ignition takes place a few milliseconds after a current pulse of at least 25 mJ is applied to the bridgewire. In contrast, as for a SCB devices, ignition takes place in a few tens of microseconds and only require approximately one-tenth the input energy of a conventional electroexplosive devices. Typically, when SCB device is driven by a short (20 $\mu\textrm{s}$), low energy pulse (less than 5 mJ), the SCB produces a hot plasma that ignites explosive materials. The advantages and disadvantages of this technology are strongly dependent upon the particular technology selected. To date, three distinct technologies have evolved, each of which utilizes a hot, silicon plasma as the pyrotechnic initiation element. These technologies are 1.) Heavily doped silicon as the resistive heating initiation mechanism, 2.) Tungsten enhanced silicon which utilizes a chemically vapor deposited layer of tungsten as the initiation element, and 3.) a junction diode, fabricated with standard CMOS processes, which creates the initial thermal environment by avalanche breakdown of the diode. This paper describes the three technologies, discusses the advantages and disadvantages of each as they apply to electroexplosive devises, and recommends a methodology for selection of the best device for a particular system environment. The important parameters in this analysis are: All-Fire energy, All-Fire voltage, response time, ease of integration with other semiconductor devices, cost (overall system cost), and reliability. The potential for significant cost savings by integrating several safety functions into the initiator makes this technology worthy of attention by the safety system designer.

• Imaging Science in Dentistry
• /
• v.40 no.4
• /
• pp.155-158
• /
• 2010

Digital radiographic systems allow the implementation of a fully digital picture archiving and communication system (PACS), and provide the greater dynamic range of digital detectors with possible reduction of X-ray exposure to the patient. This article reviewed the basic physical principles of digital radiographic imaging system in dental clinics generally. Digital radiography can be divided into computed radiography (CR) and direct radiography (DR). CR systems acquire digital images using phosphor storage plates (PSP) with a separate image readout process. On the other hand, DR systems convert X-rays into electrical charges by means of a direct readout process. DR systems can be further divided into direct and indirect conversion systems depending on the type of X-ray conversion. While a direct conversion requires a photoconductor that converts X-ray photons into electrical charges directly, in an indirect conversion, lightsensitive sensors such as CCD or a flat-panel detector convert visible light, proportional to the incident X-ray energy by a scintillator, into electrical charges. Indirect conversion sensors using CCD or CMOS without lens-coupling are used in intraoral radiography. CR system using PSP is mainly used in extraoral radiographic system and a linear array CCD or CR sensors, in panoramic system. Currently, the digital radiographic system is an important subject in the dental field. Most studies reported that no significant difference in diagnostic performance was found between the digital and conventional systems. To accept advances in technology and utilize benefits provided by the systems, the continuous feedback between doctors and manufacturers is essential.

• Journal of IKEEE
• /
• v.5 no.1 s.8
• /
• pp.111-120
• /
• 2001

VC merging involves distinguishing cells from an identical merged VC label. Various approaches have been proposed to help this identification process. However, most of them incur additional buffering, protocol overhead and/or variable delay. They make the provision of QoS difficult to achieve. So it was proposed a merge capable scheduler to support VC-merging (VCMS). However, in situations where all VCs are to be merged or the incoming traffic load is very low, it could happen that there are not enough non-merging cells to snoop. In this situation the scheduler uses special control cells to fill the empty time slots out. Too many control cells can cause high cell loss ratio and an additional packet transfer delay. To overcome the drawbacks, we propose a Sequence Skipping(SS) method where the sequencers skip the empty queues and insert SS cells. We show SS method is suitable for VC-merging and can reduce the cell loss ratio and the mean packet transfer delay through simulations.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.2
• /
• pp.343-350
• /
• 2016

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connects (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 39K at an operating frequency of 313MHz using the $0.13{\mu}m$ TSMC process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.503-506
• /
• 2015

In accordance with IoT(Internet of Things) commercialization, the need to design SoC-based hardware platform with wireless communication is increasing. This paper therefor proposes an SoC platform architecture with Smart Frame System inter-communicating between devices. Wireless communication functions and high-performance real-time image processing hardware structure was applied to existing digital photo frame. We developed a smart phone application to control the smart frame through Bluetooth communication. The SoC platform hardware consists of CIS controller, Memory controller, ISP(Image Signal Processing) module for image scaling, Bluetooth Interface for inter-communicating between devices, VGA/TFT-LCD controller for displaying video. The Smart Frame System to support the IoT services was implemented and verified using HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA. The operating frequency is 54MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.861-862
• /
• 2015

In this paper we present a low area 12-bit SAR ADC (Successive Approximation Register Analog-to-Digital Converter). The proposed circuit is fabricated using Magnachip/SK Hynix 1-Poly 6-Metal $0.18-{\mu}m$ CMOS process, and it is powered by a 1.8-V supply. Total chip area is reduced by replacing the MIM capacitors with MOS capacitors instead of the capacitors consisting of overall part in chip area. The proposed circuit showed improved power dissipation of 1.9mW, and chip area of $0.45mm^2$ as compared to conventional research results at the power supply of 1.8V. The designed circuit also showed high SNDR (Signal-to-Noise Distortion Ratio) of 70.51dB, and excellent effective number of bits of 11.4bits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.885-888
• /
• 2015

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.

• Journal of Power Electronics
• /
• v.16 no.3
• /
• pp.1226-1235
• /
• 2016

For wearable health monitoring systems, a fundamental problem is the limited space for storing energy, which can be translated into a short operational life. In this paper, a highly efficient active voltage doubling rectifier with a wide input range for micro-piezoelectric energy harvesting systems is proposed. To obtain a higher output voltage, the Dickson charge pump topology is chosen in this design. By replacing the passive diodes with unbalanced-biased comparator-controlled active counterparts, the proposed rectifier minimizes the voltage losses along the conduction path and solves the reverse leakage problem caused by conventional comparator-controlled active diodes. To improve the rectifier input voltage sensitivity and decrease the minimum operational input voltage, two low power common-gate comparators are introduced in the proposed design. To keep the comparator from oscillating, a positive feedback loop formed by the capacitor C is added to it. Based on the SMIC 0.18-μm standard CMOS process, the proposed rectifier is simulated and implemented. The area of the whole chip is 0.91×0.97 mm², while the rectifier core occupies only 13% of this area. The measured results show that the proposed rectifier can operate properly with input amplitudes ranging from 0.2 to 1.0V and with frequencies ranging from 20 to 3000 Hz. The proposed rectifier can achieve a 92.5% power conversion efficiency (PCE) with input amplitudes equal to 0.6 V at 200 Hz. The voltage conversion efficiency (VCE) is around 93% for input amplitudes greater than 0.3 V and load resistances larger than 20kΩ.