• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38B no.7
• /
• pp.564-571
• /
• 2013

Wireless network has been used in many applications due to its advantages such as convenience, mobility, productivity, easy deployment, easy expandability and low cost. When it comes to stability, wireless network still shows its limitation which makes it difficult to be used for real-time control system. One of the first problems of using wireless network for control system is clock synchronization. There have been synchronization schemes proposed for wired networked control system as well as wireless network. But these should not be applied directly in wireless network control system. In this paper, we point out the importance of clock synchronization in wireless network control system. Then based on the characteristic of wireless networked control system, we propose a clock synchronization scheme for it. Furthermore, we simulate our scheme and compare with previous synchronization scheme in wired and wireless environments.

• Molecules and Cells
• /
• v.28 no.2
• /
• pp.75-80
• /
• 2009

The cyclic environmental conditions brought about by the 24 h rotation of the earth have allowed the evolution of endogenous circadian clocks that control the temporal alignment of behaviour and physiology, including the uptake and processing of nutrients. Both metabolic and circadian regulatory systems are built upon a complex feedback network connecting centres of the central nervous system and different peripheral tissues. Emerging evidence suggests that circadian clock function is closely linked to metabolic homeostasis and that rhythm disruption can contribute to the development of metabolic disease. At the same time, metabolic processes feed back into the circadian clock, affecting clock gene expression and timing of behaviour. In this review, we summarize the experimental evidence for this bimodal interaction, with a focus on the molecular mechanisms mediating this exchange, and outline the implications for clock-based and metabolic diseases.

• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.3196-3198
• /
• 1999

In this paper, we are proposed ATM AAL 1 source clock recovery methods for CBR service. The proposed method compute the difference between network clock level and the reference level by inspecting the variation of a buffer. Also it is the service clock recovery method that control local clock using the look-up table defined clock dividing rate of the difference in advance. It can be applicable to both SDH network and PDH network which has no common reference clock between its ends, it has an important mean in view of the internetworking between existing networks for the integrated service chased by B_ISDN.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.41-44
• /
• 2001

본 논문은 액정 Driver IC에 사용되a는 내부 기준 clock 발생 및 Voltage Converter에 boosting을 하기 위한 clock을 제공하는 Oscillator 설계 및 구현 하였다 LCD Driver IC에서 발생되는 Oscillator clock 은 고속의 clock신호는 필요로 하지 않으나 LCD display에 관련된 frame 주파수에 직접적인 영향을 주므로 중심 주파수 결정 및 duty비에 따른 주파수 제어가 매우 중요하다. 본 논문에서는 가변 duty를 적용하는 LCD system에 적용할 수 있는 가변 duty oscillator를 소개한다. Process는 0.35um, 12V공정을 사용하였다.

• Journal of IKEEE
• /
• v.15 no.1
• /
• pp.23-28
• /
• 2011

This paper describes design and implementation of a spread spectrum clock generator(SSCG). The proposed architecture generates the spread spectrum clock controlling a input voltage signal for VCDL(Voltage Controlled Delay Line). Spread charge pump is controlled by the SSC modulation logic block provides a control signal to VCDL through LPF in DLL. By using this architecture, chip area and power consumption can be reduced because it is not necessary additional circuit to control modulation rate. This circuit has been designed and fabricated using the UMC 0.25um CMOS technology. The chip occupies an area of 290${\times}$120um^2.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.221-225
• /
• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.4 no.1
• /
• pp.9-16
• /
• 2008

This paper presents a frequency selection algorithm for minimization power consumption of processor in Mobile System. The proposed algorithm has processor designed low power processor using clock gating method. Clock gating method has improved the power dissipation by control main clock through the bus which is embedded clock block applying the method of clock gating. Proposed method has compared power consumption considered the dynamic power for processor, selected frequency has considered energy gain and energy consumption for designed processor. Or reduced power consumption with decreased processor speed using slack time. This technique has improved the life time of the mobile systems by clock gating method, considered energy and using slack time. As an results, the proposed algorithm reduce average power saving up to 4% comparing to not apply processor in mobile system.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.1 no.2
• /
• pp.193-197
• /
• 1997

In this paper, we propose a new PN chip clock generator which employs two synchronous counters to achieve precise phase control of chip clock. In a CDMA code acquisition and tracking system, the PN chip clock is required to operate highly reliable without any glitch even under harsh environment condition such as temperature and voltage fluctu-aliens. The digital implementation of the proposed PN chip clock generator imparts it with much desired reliability. Since the proposed chip clock generator can be easily controlled into one of the states: free running, phase advance, and delay state, it can be applied to data processing as well as code synchronization. We have done FPGA implementation of the proposed logic and have verified its satisfactory operation up to 50 MHz.

• Proceedings of the Korean Society of Agricultural Engineers Conference
• /
• 1998.10a
• /
• pp.224-229
• /
• 1998

This study was conducted to develop the simple and convenient irrigation control model which can maintain the appropriate rates of irrigation and drainage of nutrient solution according to the environmental conditions and growth stages in soilless culture of cucumber. In order to obtain fundamental data for development of the model, investigation of the actual state of soilless culture practices was carried out. Most irrigation systems of soilless culture were controlled by the time clock. Evapotranspiration of cucumber in soilless culture was investigated and correlations with environmental conditions were analyzed, and its prediction model was developed. A irrigation control model based on the time clock control and there were considered seasons, weather conditions, and growth stages was developed. Applicability of the model was tested by simulation. Drainage rates of irrigation system controlled by conventional time clock, integrated solar radiation, and the developed model were 61%, 20%, and 32%, respectively in cucumber perlite culture.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.3
• /
• pp.232-239
• /
• 2010

By using the clock timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). Compared to the authors' prior work, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The delay block generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a $0.18\;{\mu}m$ CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors' prior work, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation.