• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.337-340
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• 2001

This paper presented a new structure of RSA cryptosystem using modified Montgomery algorithm and CSA(Carry Save Adder) tree. Montgomery algorithm was modified to a radix-4 modified Booth algorithm. By appling radix-4 modified Booth algorithm and CSA tree to modular multiplication, a clock cycle for modular multiplication has been reduced to (n＋3)/2 and carry propagation has been removed from the cell structure of modular multiplier. That is, the connection efficiency of full adders is enhanced.

• 유체기계공업학회:학술대회논문집
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• 2006.08a
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• pp.383-386
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• 2006

In this study, we propose a new fast algorithm for calculating short range forces in molecular dynamics, This algorithm uses a new hierarchical tree data structure which has a high adaptiveness to the particle distribution. It can divide a parent cell into k daughter cells and the tree structure is independent of the coordinate system and particle distribution. We investigated the characteristics and the performance of the tree structure according to k. For parallel computation, we used orthogonal recursive bisection method for domain decomposition to distribute particles to each processor, and the numerical experiments were performed on a 32-node Linux cluster. We compared the performance of the oct-tree and developed new algorithm according to the particle distributions, problem sizes and the number of processors. The comparison was performed sing tree-independent method and the results are independent of computing platform, parallelization, or programming language. It was found that the new algorithm can reduce computing cost for a large problem which has a short search range compared to the computational domain. But there are only small differences in wall-clock time because the proposed algorithm requires much time to construct tree structure than the oct-tree and he performance gain is small compared to the time for single time step calculation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.64-74
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• 1999

A new clock skew optimization for clock routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevent the total wire length from increasing. As the clock skew is the major constraint for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization can increase total wire length, therefore clock routing is performed within the given skew bound which can not induce the malfunction. Clock routing under the specified skew bound can decrease total wire length Not only total wire length and delay time minimization algorithm using merging point relocation method but also clock skew reduction algorithm using link-edge insertion technique between two nodes whose delay difference is large is proposed. The proposed algorithm construct a new clock routing topology which is generalized graph model while previous methods uses only tree-structured routing topology. A new cost function is designed in order to select two nodes which constitute link-edge. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance difference is short. Furthermore, routing topology construction and wire sizing algorithm is developed to reduce clock delay. The proposed algorithm is implemented in C programming language. From the experimental results, we can get the delay reduction under the given skew bound.

• Korean Journal of Microbiology
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• v.24 no.4
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• pp.400-405
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• 1986

We have constructed a phylogenetic tree for eleven species by comparing their tRNA sequences. The tree suggests that prokaryotes diverged very early before the emergence of animals. The fact that H. volcano, an archaebacterium, clusters with eukaryotes implied that eukaryotes did not diverge directly from thier common ancestor with eubacteria. The branching order of phage $T_{4}$ and phage $T_{5}$ indicates that they have diverged separately from thier hosts and they might have evolved independently. A correlation between nucleotide substitution in tRNAs and paleontological record was observed. We verified that our phylogenetic tree fits very well with traditional ones very well by imposing the molecular clock on the tree.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.104-107
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• 2010

본 논문은 H.264/AVC 디코더의 하드웨어 구현 시 가장 많은 시간을 소비하는 부분이 움직임 추정기를 하드웨어로 구현하였다. 움직임 추정을 함에 있어서 외부메모리 Access 량을 줄이고, SAD연산을 수행할 때 Clock의 손실 없이 계산을 하는 움직임 예측기를 제안한다. 제안한 구조는 재탐색 구간에서 이전 탐색 범위와 공통부분을 이루는 부분을 레지스터에 따로 저장해 두었다가, 재탐색시에 이전 Data를 사용하는 방법을 이용하였다. 움직임 추정을 수행할 때의 SAD (Sum of absolute differences)연산 부분과 Adder-tree를 묶은 PU Array와 SAD 누적기, 선택기를 Pipelining을 통하여 Clock의 손실 없이 연속적으로 계산하는 움직임 예측기를 설계하였다. 구현한 하드웨어는 최대 446.43MHz의 주파수에서 동작할 수 있었고, 탐색영역 64${\times}$64, 참조 프레임 3, 그리고 영상크기 1920${\times}$1080 기준으로 구현한 결과 50 프레임을 처리할 수 있는 성능을 보였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• The KIPS Transactions:PartC
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• v.18C no.2
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• pp.119-126
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• 2011

In wireless sensor networks Time synchronization used to be performed after routing tree is constructed. It results in increasing the number of packets and energy consumption. In this paper, we propose a time synchronization algorithm combined with flooding routing tree construction algorithm, which applies LTS (Lightweight Time Synchronization) information packed into the forwarding and backward routing packets. Furthermore, the proposed algorithm compensates the time error due to clock drift using the round time with fixed period. We prove that the proposed algorithm could synchronize the time of among sensor nodes more accurately compared to TSRA (Time Synchronization Routing Algorithm) using NS2 simulation tool.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.838-841
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• 2007

In this study, we implemented a $17^*17b$ binary digital multiplier using radix-4 Booth's algorithm. Two stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. To evaluate the circuit, several MPW chips were fabricated using Hynix 0.6-um 3M N-well CMOS technology. Also we proposed an efficient test methodology and did fault simulations. The chip contains 9115 transistors and the core area occupies about $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.4
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• pp.206-211
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• 2005

We describe the design for a correlator and an access code generator in bluetooth system. These are used for a connection setting, a packet decision and a clock synchronization between Bluetooth units. The correlator consists of two blocks; carry save adder based on Wallace tree and threshold-value decision block. It determines on an useful packet and clock-synchronization for input signal of 1.0Mbps through the sliding-window correlating. The access-code generator also consists of two blocks; BCH(Bose-Chadhuri-Hocquenghem) cyclic encoder and control block. It generates the access-codes according to four steps' generation process based on Bluetooth standard. In order to solve synchronization problem, we make use of any memory as a pseudo random sequence. The proposed correlator and access-code generator were coded with VHDL. An FPGA Implementation of these modules and the simulation results are proved by Xilinx chip. The critical delay and correlative margin based on synthesis show the 4.689ns and the allowable correlation-error up to 7-bit.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.214-217
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• 2003

In this paper, we deal with implementing design for a correlator access code generator module which they are used for setting up a connection between units, a packet decision, a clock syncronization, by FPGA. The orrelator module which is composed of the Wallace Tree's CSA and threshold value decision device decides useful a packet and syncronizes a clock, after it correlates an input signal of 1 Mbps transmission rate by a sliding window. An access code generator module which is composed of a BCH (Bose-Chadhuri-Hocquenghem) cyclic encoder and control device was designed according as a four steps' generation process proposed in the bluetooth standard. The pseudo random sequence which solves syncronization problem saved a voluntary device Proposed the module was designed by VHDL. An simulation and test are inspected by Xilinx FPGA.