• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.10
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• pp.1004-1010
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• 2012

In this paper, we propose the algorithm which considers applying recently proposed clock synchronization techniques with quite high accuracy in a few wireless sensor networks researches to time synchronization algorithm for multi-static radar system and especially overcomes the limitation of previous theory, cannot be applied between nodes in non-line of sight (NLOS). Proposed scheme estimates clock skew and clock offset using recursive robust least M-estimator with information of time stamp observations. And we improve the performance of algorithm by tracking and suppressing the time delays difference caused by NLOS system. Futhermore, this paper derive the mean square error (MSE) to present the performance of the proposed estimator and comparative analysis with previous methods.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.379-382
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• 2000

We designed a self-timed interface circuit for efficient communication in IP (Intellectual Property)-based system with high-speed self-timed FIFO and a set of self-timed event logic library with 0.25um CMOS technology. Optimized self-timed standard cell layouts and Verilog models are generated for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. With clock control method and FIFO, we implemented high-speed 32bit-interface chip for self-timed system, which generated maximum system clock is 2.2GHz. The size of the core is about 1.1mm x 1.1mm.

• Journal of KIISE:Information Networking
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• v.32 no.6
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• pp.668-675
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• 2005

With the proliferation of wireless network and the advances of the embedded systems, the traditional distributed systems begin to include the wireless embedded systems. Clock synchronization in the distributed systems is one of the major issues that should be considered for diverse Purposes including synchronization, ordering, and consistency. Many clock synchronization algorithms have been proposed over the years. Since clock synchronization in wireless embedded systems should consider the low bandwidth of a network and the poor resources of a system, most traditional algorithms cannot be applied directly. We propose a clock synchronization algorithm in wireless embedded systems, extending IEEE 802.11 standard. The proposed algorithm can not only achieve high precision by loosening constraints and utilizing the characteristics of wireless broadcast but also provide continuous time synchronization by tolerating the message losses. In master/slave structure the master broadcasts the time information and the stave computes the clock skew and the drift to estimate the synchronized time of the master. The experiment results show that the achieved standard deviation by the Proposed scheme is within the bound of about 200 microseconds.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.12
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• pp.10-18
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• 1997

The parallel trabutary signals in the SDH-based transmission system have the frame phase skew due to uneven transmission delays in the data and the clock path. This phase skew must be eliminated prior to synchronously multiplexing process. A new twenty-four channel, 51.84Mb/s DFPA(Digital Frame Phase Aligner) has been designed and fabricated in 0.8.mu.m CMOS gate array. This unique device phase-aligns the skewed input signals with refernce frame synchronous signal and reference clok for subsequent synchronous multiplexing process. the performance of fabricated device is evaluated by the STM-16 transmission system and DS-3 meansurement set. The frame phase margin of +2/-3 bit periods has been demonstrated.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.68-70
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• 1998

본 논문에서는 클록들을 주기적으로 동기화하는 분산 실시간 시스템에서 주어진 태스크의 시간 제약(timing constraint)을 변환시는 구가지 기법을 제안한다. 전형적인 이산 클록 동기화(discrete clock synchronization)알고리즘은 클록의 값을 순간적으로 보정(correct)하여 클록의 시간이 불연속적으로 진행학 한다. 이러한 시간상의 불연속성은 태스크의 시작제한시간(release time)이나 종료시한(deadline)과 같은 이벤트를 잃어버리거나 다시 발생시키는 오류를 범하게 한다. 클록 시간의 불연속성을 피하기 위해 일반적으로 연속 클록 동기화(continuous clock synchronization) 기법이제안되었지만 소프트웨어적으로 구현되기에는 많은 오버헤드를 유발시키는 문제점이 있다. 이에 따라 연속 클록 동기화는 PLL (Phase-Locked Loop)을 이용한 별도의 하드웨어를 사용하는 것이 보통이다. 본 논문에서는 연속 클록 동기화 기법을 사용하는 대신, 태스크의 시간 제약을 동적으로 변환시키는 DCT (Dynamic Constraint Transformation) 기법을 제안하였다. DCT는 소프트웨어 으로 구현이 가능하여 새로운 하드웨어를 필요로 하지 않으며, 이를 통해 기존의 이산적으로 동기화된 시스템에서 클록 시간의 불연속성에 의한 문제점들을 해결할 수 있다. 또 다른 문제점으로서, 클록의 물리적인 특성으로 인해 동기화된 클록들이 상한된(bounded from the above)오차(skew)를 갖는다는 것이다. 이러한 오차는 지역 클록(local clock)에 대해 만족될 수 있는 임의의 실기간 제약 조건이 전역 클록(global clock)에 대해서는 만족되지 않을 수 있음을 의미한다. 본 논문에서는 이를 위해 먼저 두 가지의 스케줄링 가능성, 지역적 스케줄링 가능서(local schedulability)과 전역적 스케줄링 가능성(global schedulability)을 정의하고, 실시간 제약을 정적으로 변환시키는 SCT (Static Constraint Transformation)기법을 제안하였다. SCT를 통해 지역적으로 스케줄링 가능한 태스크는 전역적으로 스케줄링이 가능하므로, 단지 지역적 스케줄링 가능성만을 검사하면서 스케줄링 문제를 해결할 수 있도록 하였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.7
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• pp.17-26
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• 1999

In this paper, Bit selectable and Bi-directional Interface Device is described, which can communicate data with the peripheral devices. Specially, an algorithm of truth-table comparison that synthesizes the pulse-type sequential circuit pulse has been proposed to design the Interrupt Generator, and implemented in designing the Interrupt Register. Also, a description of the asynchronous design method is given to remove the clock skew phenomenon, and the output asynchronous control method which finds the optimal clock and controls all the enable signal of the output pins at the same time is presented. Using this technique interface ports have delay time of less-than 0.7ns.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.1035-1037
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• 2012

무선 센서네트워크에서의 시각동기는 MAC 계층에서부터 APP 계층에 이르기까지 거의 모든 계층에서 다양한 목적을 위해 매우 중요한 기술이다. 본 논문에서는 무선 센서네트워크에서의 에너지 효율적인 시각동기를 위한 실시간 클럭 스큐 추정 방법을 제시한다. 재귀적 최소제곱법을 통해 오프셋 보정 정보들을 얻을 때마다 클럭 스큐가 실시간적으로 추정 및 갱신되며, 아울러 스큐 추정을 위해 각 센서노드에 저장해야할 정보를 최소화한다. 제안한 클럭 스큐 추정 방법은 기존의 클럭 오프셋 보정 방법과 쉽게 통합될 수 있으며, 이 경우 보다 정확하고 효율적인 시각동기화가 가능해진다. 시뮬레이션 및 실험 결과를 통해 제안한 클럭 스큐 추정 방법을 통한 시각동기 정확도의 향상을 보인다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.433-448
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• 2012

A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weight-adjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only $0.152mm^2$ and consumes 69.8 mW, while the rest of the receiver occupies $0.297mm^2$ and consumes 56.0 mW at the 7- Gb/s data-rate and supply voltage of 1.35 V.