• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.293-296
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• 2007

In this paper, we propose the systolic array architecture for the vector median filter. In the color image processing, the vector signal (i.e. the color) consists of three elements, red, green and blue. The vector median filter is very effective to utilize the correlation among red, green and blue elements. The computational complexity of the proposed architecture for computing the vector median of N vector signals is (N+2) clock periods compared to the (3N+1) clock periods in the previous method. In addition to, the input vector signals can be loaded in serial in the proposed architecture. In the previous method, N input vector signals should be loaded to the vector median filter in parallel at the first clock. The proposed architecture is implemented with FPGA.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.20-23
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• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

• Korean Journal of Optics and Photonics
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• v.3 no.2
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• pp.123-132
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• 1992

We designed and constructed the Cs beam tube which consists of a Ramsey cavity, four C-field rods, fluorescence detecting systems, and etc. for developing an optically pumped Cs atomic clock. A semiconductor laser was used for optical pumping and probing in the Cs beam. We observed Ramsey resonance signal by detecting the fluorescence signal in the probing region as the microwave frequency injected into the Ramsey cavity was scanned near 9192.6 MHz which corresponds to the "clock transition" of Cs atoms. We found that the linewidth of the Ramsey signal was 200 Hz, the magnetic field intensity was $8.61\muT$ when the current of 0.8A flowed in the C-field rods, and the second order Zeeman shift by the magnetic field was 3.17 Hz.s 3.17 Hz.

• The KIPS Transactions:PartC
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• v.18C no.1
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• pp.7-14
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• 2011

Power analysis attack on low-power consumed security devices such as smart cards is very powerful, but it is required that the correlation between the measured power signal and the mid-term estimated signal should be consistent in a time instant while running encryption algorithm. The power signals measured from the security device applying the random clock do not match the timing point of analysis, therefore random clock is used as counter measures against power analysis attacks. This paper propose a new constant pitch based time alignment for power analysis with random clock power trace. The proposed method neutralize the effects of random clock used to counter measure by aligning the irregular power signals with the time location and size using the constant pitch. Finally, we apply the proposed one to AES algorithm within randomly clocked environments to evaluate our method.

• Korean Journal of Optics and Photonics
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• v.16 no.1
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• pp.21-26
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• 2005

10 GHz clock recovery from 40 Gbit/s optical time-division-multiplexed(OTDM) signal pulses was experimentally demonstrated using an optical phase lock loop based on a terahertz optical asymmetric demultiplexer(TOAD) with a local-reference-oscillator-free electronic feedback circuit. The 10 GHz clock was successfully extracted from 40 Gbit/s signals. The SNR of the time-extracted 10 GHz RF signal to the side components was larger than 40 dB. Also we performed numerical simulation about the extraction process of phase information in TOAD. The lock-in frequency range of the clock recovery is found to be 10 kHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.171-177
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• 2006

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.3
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• pp.225-231
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• 2011

The satellite clock anomalies, one of the abnormal signal factors of the GPS satellites, can have a significant impact on the GPS measurements. However, it can be difficult to detect the anomalies of the satellites clock before the range of the satellites clock error becomes bigger than the range of the other factors, due to the measurement including error of the orbit, ionosphere delay, troposphere delay, multipath and receiver clock. In order to perform quick and accurate detection by minimization of critical range in anomalies of the satellites clock, this paper suggested a solution to detect precise anomalies of the satellites clock after application of carrier smoothing filter from measurement by dual-frequency and adjustment of errors which can be occurred by other factor and the receiver clock errors. The performance of the proposed method was confirmed by comparing to the satellite clock biases which are provided by IGS.

• Molecules and Cells
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• v.39 no.1
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• pp.6-19
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• 2016

Redox signalling comprises the biology of molecular signal transduction mediated by reactive oxygen (or nitrogen) species. By specific and reversible oxidation of redoxsensitive cysteines, many biological processes sense and respond to signals from the intracellular redox environment. Redox signals are therefore important regulators of cellular homeostasis. Recently, it has become apparent that the cellular redox state oscillates in vivo and in vitro, with a period of about one day (circadian). Circadian timekeeping allows cells and organisms to adapt their biology to resonate with the 24-hour cycle of day/night. The importance of this innate biological timekeeping is illustrated by the association of clock disruption with the early onset of several diseases (e.g. type II diabetes, stroke and several forms of cancer). Circadian regulation of cellular redox balance suggests potentially two distinct roles for redox signalling in relation to the cellular clock: one where it is regulated by the clock, and one where it regulates the clock. Here, we introduce the concepts of redox signalling and cellular timekeeping, and then critically appraise the evidence for the reciprocal regulation between cellular redox state and the circadian clock. We conclude there is a substantial body of evidence supporting circadian regulation of cellular redox state, but that it would be premature to conclude that the converse is also true. We therefore propose some approaches that might yield more insight into redox control of cellular timekeeping.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.