• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.10
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• pp.79-88
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• 2003

We demonstrate a novel all-optical packet switching system that is suitable for optical ring networks. For the demonstration, video signals are encoded into optical packets which are composed of header and payload. The optical packets are all-optically processed at a switching node based on all-optical header processor, packet-level clock extraction, bit-level clock extraction, all-optical data format converter and so on.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.9
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• pp.1343-1349
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• 2013

In optical fiber communications, several newly-developed signal formats are used to obtain the best performance within limited spectral bandwidth. CSRZ (carrier-suppressed return-to-zero) format is one of the new signal formats, which has better spectral efficiency and better robustness to dispersion than RZ (return-to-zero) format. Thus it is widely used for demonstrating high-speed optical communication systems. In an earlier research, we proposed a clock-extraction method of CSRZ signal to monitor chromatic dispersion. However, the clock-frequency component extracted by the clock-extraction method can be affected by the bandwidth of a transmitter or a receiver. Therefore, in this paper, we investigate the effect of bandwidth on the chromatic dispersion monitoring of CSRZ signal based on clock-frequency component. As a result, we propose a couple of robust clock-extraction methods to monitor chromatic dispersion in CSRZ signal.

• Journal of the Optical Society of Korea
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• v.16 no.3
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• pp.215-220
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• 2012

In an earlier work, we proposed the chromatic dispersion monitoring technique of non-return to zero (NRZ) signal based on clock-frequency component (CFC) through numerical simulations. However, we have not yet shown any experimental demonstration or analytic derivation of it. In this paper, we show an experimental demonstration and analytic derivation of the proposed chromatic dispersion monitoring technique. We confirm that the experimental results and the analytic results correspond with the simulation results. We also demonstrate that monitoring range and accuracy can be improved by using a simple clock-extraction method.

• ETRI Journal
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• v.30 no.3
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• pp.461-468
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• 2008

This paper presents a chromatic dispersion monitoring technique using a clock-frequency component for carrier-suppressed return-to-zero (CSRZ) signal. The clock-frequency component is extracted by a clock-extraction (CE) process. To discover which CE methods are most efficient for dispersion monitoring, we evaluate the monitoring performance of each extracted clock signal. We also evaluate the monitoring ability to detect the optimum amount of dispersion compensation when optical nonlinearity exists, since it is more important in nonlinear transmission systems. We demonstrate efficient CE methods of CSRZ signal to monitor chromatic dispersion for optimum compensation in high-speed optical communication systems.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.1-9
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• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• Proceedings of the Optical Society of Korea Conference
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• 1999.08a
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• pp.94-95
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• 1999

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.249-254
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• 2001

A receiver ASIC for fiber optic modules of STM-1 optical communication has been fabricated with 0.65 $\mu\textrm{m}$ CMOS technology. The ASIC has a limit amplifier circuit for the 155.52 Mbps data reshaping, and a clock extraction circuit for the 155.52 MHz clock recovery. The ASIC has an acquisition aid and LOS monitoring circuit for properly operation with near 155.52 MHz clock frequency in case of the data loss due to transmission line open or data transfer fail. Measured results show that the circuit reshapes data from 5 mV to 1 V wide range of input voltage condition, add it recovers system clock with stable on any condition.

• Korean Journal of Optics and Photonics
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• v.16 no.1
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• pp.21-26
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• 2005

10 GHz clock recovery from 40 Gbit/s optical time-division-multiplexed(OTDM) signal pulses was experimentally demonstrated using an optical phase lock loop based on a terahertz optical asymmetric demultiplexer(TOAD) with a local-reference-oscillator-free electronic feedback circuit. The 10 GHz clock was successfully extracted from 40 Gbit/s signals. The SNR of the time-extracted 10 GHz RF signal to the side components was larger than 40 dB. Also we performed numerical simulation about the extraction process of phase information in TOAD. The lock-in frequency range of the clock recovery is found to be 10 kHz.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.697-700
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• 1988

This paper describes the design of a hardware system for ECG feature extraction based on pipeline processor consisting of three computers. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggred detector. Four diagnostic parameters-heart, axis, and ST axis, and ST segment are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. Therefore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory units is designed to decrease the delay time caused by data transfer between processors and designed by which the delay time can be taken 1% of one clock period.