• Journal of Advanced Navigation Technology
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• v.20 no.6
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• pp.631-637
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• 2016

Quantum cellular automata (QCA) are one of the alternative technologies that can overcome the limits of complementary metal-oxide-semiconductor (CMOS) scaling. It consists of nano-scale cells and demands very low power consumption. Various circuits on QCA have been researched until these days, and in the middle of the researches, exclusive-OR (XOR) gates are used as error detection and recover. Typical XOR logic gates have a lack of scalable, many clock zones and crossover designs so that they are difficult to implement. In order to overcome these disadvantages, this paper proposes XOR design using majority gate reduced clock zone. The proposed design is compared and analysed to previous designs and is verified the performance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1666-1671
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• 1989

A novel switched-capacitor circuit for interfacing capacitive microtransducers with a digital system is developed based on the dual-slope integration. It consists of a differential integrator and a comparator. Driven by the teo phase clock, the circuit first senses the capacitance difference between the transducer and the reference capacitor in the form of charge, and accumulates it into the feedback capabitor of the integrator for a fixed period of time. The resulant accumulated charge is next extracted by the known reference charge until the integrator output voltage refurns to zero. The length of time required for the integrator output to return to zero, as measured by the number of clock cycle gated into a counter is proportional to the capacitance difference, averaged over the integration period. The whole operation is insensitive to the reference voltage and the capacitor values involved in the circuit, Thus the proposed circuit permits an accurate differental capacitance measurement. An error analysis has showh that the resolution as high as 8 bits can be expected by realizing the circuit in a monolithic MOS IC form. Besides the accuracy, it features the small device count integrable onto a small chip area. The circuit is thus particularly suitadble for the on-chip interface.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.6
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• pp.910-915
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• 2018

The precise time, which is an essential element of the Global Navigation Satellite System (GNSS), such as US GPS, GLONASS in Russia, Galileo in Europe, and Beidou in China, is an important foundation for various economic activities around the world. Communication systems, power grids, IoT, Cloud computing and financial networks operate based on the precise time not only for the operating principles, but also for the synchronization and operational efficiency between tasks. In this paper, we introduce the Atomium software for the first time in South Korea. Atomium was developed by ORB in Belgium to calculate the clock error(clock solution) with GNSS signal observation data based on PPP method. The observation data is provided by Korea Research Institute of Standards and Science(KRISS). The results of MJD57106 with Atomium software are presented.

• Aerospace Engineering and Technology
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• v.3 no.1
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• pp.109-116
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• 2004

In a satellite time management system, the GPS-based clock synchronization technique[1] has the merits of precision time management by knowing the time difference or the error between the OBT(On Board Time) of the internal processors and GPS time every second. It can be realized employing the DPLL(Digital Phase Loop Lock) and FEP(Front End Processor) circuitry for the clock synchronization[2]. In this paper, a refined DPLL & FEP scheme is proposed to provide the precision, stability and robustness of the operation, which is to compensate the errors and noise of the GPS signal, and also to cope with the case when the GPS signal is lost due to several reasons. The simulation and HIL (Hardware In the Loop) test results using the FM(Flight Model) in the course of KOMPSAT-2(Korea Multi Purpose Satellite-2) design and development are illustrated to demonstrate the salient features of this methodology.

• ETRI Journal
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• v.33 no.3
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• pp.326-334
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• 2011

This paper outlines the time jitter effect of a sampling clock on a software-defined radio technology-based digital intermediate frequency (IF) transceiver for a mobile communication base station. The implemented digital IF transceiver is reconfigurable to high-speed data packet access (HSDPA) and three bandwidth profiles: 1.75 MHz, 3.5 MHz, and 7 MHz, each incorporating the IEEE 802.16d worldwide interoperability for microwave access (WiMAX) standard. This paper examines the relationship between the signal-to-noise ratio (SNR) characteristics of a digital IF transceiver with an under-sampling scheme and the sampling jitter effect on a multichannel orthogonal frequency-division multiplexing (OFDM) signal. The simulation and experimental results show that the SNR of the OFDM system with narrower band profiles is more susceptible to sampling clock jitter than systems with relatively wider band profiles. Further, for systems with a comparable bandwidth, HSDPA outperforms WiMAX, for example, a 5 dB error vector magnitude improvement at 15 picoseconds time jitter for a bandwidth of WiMAX 3.5 MHz profile.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.3
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• pp.91-98
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• 2015

As one of solutions to obtain efficient use of limited spectrum resource, we suggest a methodology for the co-channel multi-site radar operations with a shifted linear frequency modulation (SLFM) based on GPS clock. The proposed algorithm is that we find a candidate set of SLFM signals with the minimum acceptable level of the correlation from the cross-correlation characteristics among selected SLFM signals. To verify the proposed methodology, numerical analysis has been accomplished for several radars operating in the same channel with a sawtooth or triangle LFM signal. The computational results of detected distances as well as range profiles are also examined for interference, noise, and algorithm limitation including the error of clock synchronization.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.8-14
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• 2013

A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5A
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• pp.561-570
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• 2008

Time synchronization is essential for a number of network applications such as high speed communication and parallel/distribution processing systems. As the era of ubiquitous computing is ushered in, the high precise time synchronization in wireless networks have been required in. This paper presents the design ana the implementation of the high precision time synchronization in wireless networks using ZigBee. To achieve high precision requirements, we have tried to analyze and reduce error factors such as the latency and jitters of a protocol stack on wireless environments. In addition, this paper includes some experiments and performance evaluations of our system. The result is that we established for nodes in a network to maintain their elects to within a 50 nanosecond offset from the reference clock.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.9
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• pp.941-946
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• 2011

The Loran-C, a radio navigation system based on TDOA measurements is enhanced to eLoran using TOA measurements instead of TDOA measurements. Many error factors such as PF, SF, ASF, clock errors and unknown biases are included in eLoran TOA measurements. Because these error factors can cause failure in eLoran navigation algorithm, these errors must be compensated for high accuracy eLoran navigation results. Compensation of ASF and unknown biases are difficult to calculate, while the others such as PF and SF are relatively easy to eliminate. In order to compensate all errors in eLoran TOA measurements, a simple GPS aided bias compensation method is suggested in this paper. This method calculates the bias as the difference of TOA measurement and the range between eLoran transmitters and the receiver whose position is determined using GPS. The real data measured in Europe are used for verification of suggested method and navigation algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.681-684
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• 2008

Bluetooth baseband performs FEC (forward error check) at the interface of transmitter and receiver modem. Well-designed FEC means directly the efficiency of retransmission of the data payload therefore design optimization is very important. In this paper, we designed a optimal 1/3, 2/3 type of FEC. 1/3 FEC. which performs 3 times customary repetition was designed for packet header, and 2/3 FEC was designed for data packets with (15, 10) reduced hamming code. The proposed hardware FEC block was described and verified using Verilog HDL and later to be automatically synthesized. The synthesized FEC block operated at 40Mhz normal clock speed of the target baseband microcontroller.