• Journal of the Korean Society for Aviation and Aeronautics
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• v.21 no.1
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• pp.8-14
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• 2013

As GNSS(Global Navigation Satellite System) is used in various filed, many countries establish GNSS system independently. But GNSS system has the limitation of accuracy and stability in stand-alone mode, because this system has error elements which are ionospheric delay, tropospheric delay, orbit ephemeris error, satellite clock error, and etc. For overcome of accuracy limitation, the DGPS(Differential GPS) and RTK(Real-Time Kinematic) systems are proposed. These systems perform relative positioning using the reference and user receivers. ETRI(Electronics and Telecommunications Research Institute) is developing precision navigation system in point of extension of GNSS usage. The precision navigation system is for providing the precision navigation solution to common users. If this technology is developed, GNSS system can be used in the fields which require precision positioning and control. In this paper, we introduce the precision navigation system and perform design and algorithm verification.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.109-114
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• 2004

A new code and its decoding scheme are proposed. With this code, we can correct and detect the errors in communication systems. To limit the runlength of data 0 and augment the minimum density of data 1, a (15, 7) BCH code is modified and an overall parity bit is added. The proposed code is a (16, 7) block code which has the bit clock signal regeneration capability and high error control capability. It is proved that the runlength of data 0 is less than or equal to 7, the density of data 1 is greater than or equal to 1/8, and the minimum Hamming distance is 6. The decoding error probability, the error detection probability and the correct decoding probability are presented for the proposed code. It is shown that the proposed code has better error control capability than the conventional schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.164-167
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• 2000

This paper introduces the design of high-speed analog-to-digital converter for hard disk drive (HDD) read channel. This is based on autozero technique for low-error rate, and Double Speed Dual ADC(DSDA) technique lot efficiently increasing the conversion speed of A/D converter. This An is designed by 6bit resolution, 800M sample/s maximum conversion rate, 390㎽ power dissipation, one clock cycle latency in 0.65 $\mu\textrm{m}$ CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2160-2169
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• 1994

Main components of phase time error of synchronous network are flicker noise and random walk noise. This paper describe computer simulation of clock error characterized by a statistical model recommended as a standard measure. Flicker noise sequences are generated from white noise sequences by means of a algorithm developed by Barnes. Random-walk noise sequence are obtained by integration of a white noise sequence. Especially for flicker noise, relation between stage number N, time constant ratio K and bandwidth of flicker noise generated was defined by using some examples.

• Journal of Positioning, Navigation, and Timing
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• v.11 no.4
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• pp.251-261
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• 2022

The Centimeter Level Augmentation Service (CLAS) is the Precise Point Positioning (PPP) - Real Time Kinematic (RTK) correction service utilizing the Quasi-Zenith Satellite System (QZSS) L6 (1278.65 MHz) signal to broadcast the Global Navigation Satellite System (GNSS) error corrections. Compact State-Space Representation (CSSR) corrections for mitigating GNSS measurement error sources such as satellite orbit, clock, code and phase biases, tropospheric error, ionospheric error are estimated from the ground segment of QZSS CLAS using the code and carrier-phase measurements collected in the Japan's GNSS Earth Observation Network (GEONET). Since the CLAS service begun on November 1, 2018, users with dedicated receivers can perform cm-level precise positioning using CSSR corrections. In this paper, CLAS-based VRS-RTK performance evaluation was performed using Global Positioning System (GPS) observables collected from the refence station, TSK2, located in Japan. As a result of performing GPS-only RTK positioning using the open-source software CLASLIB and RTKLIB, it took about 15 minutes to resolve the carrier-phase ambiguities, and the RTK fix rate was only about 41%. Also, the Root Mean Squares (RMS) values of position errors (fixed only) are about 4cm horizontally and 7 cm vertically.

• ETRI Journal
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• v.26 no.6
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• pp.657-660
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• 2004

We propose a fine phase tuner and a rounding processor for a numerically controlled oscillator (NCO), yielding a reduced phase error in generating a digital sine waveform. By using the fine phase tuner presented in this paper, when the ratio of the desired sine wave frequency to the clock frequency is expressed as a fraction, an accurate adjustment in representing the fractional value can be achieved with simple hardware. In addition, the proposed rounding processor reduces the effects of phase truncation on the output spectrum. Logic simulation results of the NCO using these techniques show that the noise spectrum and mean square error (MSE) for eight output bits of a 3.125 MHz sine waveform are reduced by 8.68 dB and 5.5 dB, respectively, compared to those of the truncation method, and 2.38 dB and 0.83 dB, respectively, compared to those of Paul's scheme.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.1
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• pp.12-18
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• 2008

In this research, we proposed a method for high precision measurement than laser displacement measurement. The proposed method finds the causes of error due to change in reflected laser signal level reflected from an object and compensation, and we designed this by applying laser displacement meter.

• Journal of electromagnetic engineering and science
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• v.17 no.1
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• pp.39-43
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• 2017

In this paper, a systematic and statistical calibration technique was implemented to calibrate a high-speed signal converting system containing multiple digital-to-analog converters (DACs). The systematic error (especially the imbalance between DACs) in the current combining network of the multi-DAC system was modeled and corrected by calculating the path coefficients for individual DACs with wideband reference signals. Furthermore, by applying a Kalman filter to suppress noise from quantization and clock jitter, accurate coefficients with minimum noise were identified. For correcting an arbitrary waveform generator with two DACs, a co-simulation platform was implemented to estimate the system degradation and its corrected performance. Simulation results showed that after correction with 4.8 Gbps QAM signal, the signal-to-noise-ratio improved by approximately 4.5 dB and the error-vector-magnitude improved from 4.1% to 1.12% over 0.96 GHz bandwidth.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.306-312
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• 2000

In this paper, the efficient architecture of small Reed-solomon architecture is suggested. Here, 3-stage pipeline is adopted. In decoding, error-location polynomials are obtained by BMA using fast iteration method, and syndrome polynomials, where calculation complexity is required, are obtained by parallel calculation using ROM table, and the roots of error location polynomial are calculated by ROM table using Chein search algorithm. In the suggested decoder, it is confirmed that 3 symbol random errors can be corrected and 124Mbps decoding rate is obtained using 25 Mhz system clock.